Browse Prior Art Database

Memory Architecture for Implementing Multiple Decode Schemes

IP.com Disclosure Number: IPCOM000235866D
Publication Date: 2014-Mar-28
Document File: 6 page(s) / 465K

Publishing Venue

The IP.com Prior Art Database

Abstract

With increase in demand for lot of applications in all electronic gadgets, demand for internal storage memory with wider data and word depth is increasing. SRAM’s are preferred as storage cells because of its higher processing speed. SRAM macro is designed putting together array of 6T cells with some periphery logic to enable reading from the cell and writing into the cell. Periphery not scaling to the same percentage as SRAM cells made designing SRAM macros with wider bits and words area in-efficient. We implement larger data widths with lower column muxing at sense-amplifier and write driver. In this paper we present an architecture which uses higher column muxing scheme to realize lower column muxing scheme. Proposed architecture is better in area and either same or better with respect to global bitline switching power. We will discuss area and power comparison results using 32nm SOI SRAM Compiler. This architecture can be further extended to any array based design.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 52% of the total text.

Page 01 of 6

Memory Architecture for Implementing Multiple Decode Schemes


I. Introduction

Designing SRAM's with lower column muxing has put up with many challenges. Supporting lower decodes (muxing) with cell width scaling but periphery not scaling by similar percentage is not area efficient for layout. Supply (possibly smaller width) and Signal routing tracks planning going to be tough and might increase area to accommodate. Increased challenge in providing Charge damage ring (static charges discharge path from diffusion) connection within M2 level. Exiting the Input and Output pins will be of concern. Coupling seen on all of the control signals going into Read/Write Circuits increases with increased switching per bit.

Before we discuss about proposed architecture, we will review through present available architectures. For example to design 8 Bit, 256 Words memory instance, 2 possible architectures are possible. One using 2 to1 column muxing and the other with 4 to1 muxing 2 instances of 4 bits designs.

Fig 1: 8 Bit, 256 Words Memory instance (Column Mux 2)

1


Page 02 of 6

Fig 2: 2 Memory instances of 4 Bit and 256 Words (Column Mux 4)

Fig 3: Color coding of the blocks for Fig 1 and 2

In the above 2 architectures we will have single Wordline (row) turned on during memory access. At a time all the sense amplifiers or write drivers are ON.

We have 2 proposals to design lower decode scheme using higher decode. Both has its advantages and disadvantages. We will discuss more in section 2 and 3.


II. Proposal 1 with Multi-Bank

In this proposal we have divided rows into 2 banks with 128 rows per bank. BitSlice is with 4 to 1 column muxing (4 column pitch). In normal scenario we will turn on one Wordline per instance. But in the proposed architecture we will turn ON 2 wordlines, one in Bank0 and other equivalent one from Bank1. In one operation BitSlice0 and BitSlice1 are turned ON and generate 2 outputs in 4 column pitch i.e., effectively 1 bit of 2 column pitch.

2


Page 03 of 6

Fig 4: Proposal 1 with 2 banks approach

In proposal 1 architecture, local bitlines (bitline and bitline bar) are shorter, but global bitlines (RGBLC) are longer. Less number of cells connected to bitline (CPBL), so better performance. In the case of 4 to 1 mux design, one full bank is put in retention mode (power saving mode). And only half the global bitlines contribute to switching power. This scheme is little area in-efficient. We will see increase in Read and Write switching power as global b...