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Apparatus and Method to reduce peak power consumption while running ATPG patterns

IP.com Disclosure Number: IPCOM000235871D
Publication Date: 2014-Mar-28
Document File: 6 page(s) / 54K

Publishing Venue

The IP.com Prior Art Database

Abstract

During ATPG test process, patterns are shifted in during a scan phase. During capture phase, a capture pulse is applied to excite functional paths and capture logic values in flops. Typically, all the flops of a design are pulsed at the same time, creating a very high power consumption in a chip. Multiple such patterns cause this situation many times during the course of running ATPG patterns. Power consumption during ATPG can be significantly higher compared to peak power consumption in functional mode. This can cause undesirable IR droop, failure of patterns leading to yield loss when the reason for failure is not an actual fault but IR droop caused by the pattern, and also potential damage and accelerated aging in the chip. Existing measures such as testing only a part of the design at a time can reduce peak power consumption, but have the disadvantages of increased test time because logic that could have been tested simultaneously are now tested separately, with scan and capture cycles to be done all over again across blocks. Existing methods also have alternative solutions, such as giving multiple capture pulses to the design, each pulse toggling only a limited part of the design. This falls under sequential ATPG. This is not efficient, even though common ATPG tools can generate patterns with this scheme. The number of patterns is very large, and meeting coverage targets is always a challenge, leading to high TAT and low coverage. Combinational patterns generate high coverage efficiently. But, they need all captures to happen at the same time, with a single capture pulse. There is a need to make combinational patterns work in a multiple capture pulse scenario so that only a part of the entire design would be pulsed at a time, reducing the peak power consumption significantly. The methos detailed here describes circuit design and the mathematical framework and algorithm to make a design work in a combinational ATPG mode, yet with multiple capture pulses, achieving high coverage and low peak power consumption, without sacrificing test time

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Apparatus and Method to reduce peak power consumption while running ATPG patterns

High power consumption during capture phase of ATPG

During ATPG test process, patterns are shifted in during a scan phase. During capture phase, a capture pulse is applied to excite functional paths and capture logic values in flops. Typically, all the flops of a design are pulsed at the same time, creating a very high power consumption in a chip. Multiple such patterns cause this situation many times during the course of running ATPG patterns.

Power consumption during ATPG can be significantly higher (x2 times in theory and much higher in observed results) in chips compared to peak power consumption in functional mode. This can cause immense stress on the power lines, undesirable IR droop, failure of patterns leading to yield loss when the reason for failure is not an actual fault but IR droop caused by the pattern, and most importantly potential damage and accelerated aging to the chip.

Representation of logic dependency in chains

Say there are n scan chains and m flops in each scan chain. A dependency matrix can be created as

a1 = c11*a1 + c12*a2 + …c1i*ai.. + c1n*an

a2 = c21*a1 + c22*a2 + …c2i*ai.. + c2n*an ……………equation(1)

……

an = cn1*a1 + cn2*a2 + …cni*ai.. + cnn*an

This matrix can be used to denote dependencies. cij is either '0' or '1' . For example,

a5 = a1 + a2 + a4 means there is at least one flop in chain number 1, 2 and 4 that drive a data pin or combinational logic converging to at-least one flop in chain 5.

In general, if cxy is 1, it means there are paths from flops in chain number y to chain number x. Essentially, this means, chain number x should be pulsed during the capture phase of ATPG to capture effects created by chain number y ………statement (1)

Representation of logic dependency in chains ..contd..

Additionally, each non-zero coefficient can be represented as below, where cijk = 0 or 1,

1


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m being the number of flops in each chain (assumed to be constant in this discussion)

c11 = [ c111 c112 c113 … c11m] ; (c11 != 0)

c12 = [ c121 c122 c123 … c12m] ; (c12 != 0)

….

c1n = [ c1n1 c1n2 c1n3 … c1nm] ; (c1n != 0)

---------------------------------------------------------------

c21 = [ c211 c212 c213 … c21m] ; (c21 != 0)

c22 = [ c221 c222 c223 … c22m] ; (c22 != 0)

….

c2n = [ c2n1 c2n2 c2n3 … c2nm] ; (c2n != 0)

---------------------------------------------------------------

cn1 = [ cn11 cn12 cn13 … cn1m] ; (cn1 != 0)

cn2 = [ cn21 cn22 cn23 … cn2m] ; (cn2 != 0)

….

cnn = [ cnn1 cnn2 cnn3 … cnnm] ; (cnn != 0)

---------------------------------------------------------------

Reducing peak power in capture phase through multiple captures

Through staggered capture pulses, only a part of the design is toggled at a time, reducing the peak power consumption significantly

A pattern generated to work in a single capture pulse scenario (referred to as combinational ATPG) cannot be used for...