Browse Prior Art Database

Speculative Resource Allocation in Asynchronous Simultaneous Multithreading Computing Instruction Streams

IP.com Disclosure Number: IPCOM000235936D
Publication Date: 2014-Mar-31
Document File: 5 page(s) / 293K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a mechanism to allocate resources in a high-speed computing system on a per-thread basis to minimize the performance impact across threads in a multithreaded computer system. When a particular thread becomes resource-constrained, the mechanism allows the other thread(s) to proceed unconstrained.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 37% of the total text.

Page 01 of 5

Speculative Resource Allocation in Asynchronous Simultaneous Multithreading Computing Instruction Streams

For high-speed computing systems, resource allocation may be decided speculatively, prior to knowing whether resources are required. Since the prediction is not always correct, some performance penalty is incurred; resources are sometimes allocated

when not needed.

A particular example in microarchitecture involves Control Instructions, such as SET

ADDRESS SPACE CONTROL (SAC) or SET ADDRESS SPACE CONTROL FAST (SACF). In certain cases, Control Instructions such as these indicate that subsequent instructions require additional hardware resources. In other cases, no additional resources are required. Since the resolution of the instruction is not known early enough, resources are allocated to provide for the worst case.

The novel contribution is a mechanism to allocate resources on a per-thread basis to minimize the performance impact across threads in a multithreaded computer system. When a particular thread becomes resource-constrained, the mechanism allows the other thread(s) to proceed unconstrained.

Control Instructions, such as SAC and SACF, may update the machine state, such the addressing space bits in a Control Register. For Access Register (AR)-mode addressing mode, the base register used for address generation for memory accesses specifies the base general register and the base address register. For example, an L

with B2=5 requires the General Purpose Register (GPR)-5 and AR-5 as sources for the memory access.

In the existing design, each dispatch pipe can specify four logical-registers (or lregs) as sources and a target taking into account the Base-AR as a potential source. In the novel design, the number of lregs per dispatch pipe is dropped to three, and a source stealing is required if the number of lregs required exceeds three.

In the existing design, speculatively assuming AR-mode does not affect the instruction grouping because sufficient resources are available on each pipe. In the novel design, speculatively assuming AR-mode limits the group size to two instructions, since each dispatch pipe has a limited number of resources to fit the additional AR-reg source.

Since the penalty is higher now than in the past, a more accurate, thread-based tracking mechanism is preferred.

In an exemplary embodiment, an Instruction Decode Unit (IDU), as depicted the drawings, is capable of servicing two threads. Referring to Figure 1, the unit has a Streaming Buffer (100), which contains raw Instruction Text, representing instructions in the enterprise system architecture. These instructions are read out and stored, along

with related data, in an Instruction Queue (INQ) (101). The INQ is statically divided,

with half of the entries reserved for each of the two threads. Thread Switching Logic,

1


Page 02 of 5

(102) subsequently reads Instruction data out of the INQ, according to which thread the processor is currently executing....