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Calibration Method for Guaranteeing LO Chain Functionality & Performance while Reducing Power Consumption

IP.com Disclosure Number: IPCOM000235944D
Publication Date: 2014-Mar-31
Document File: 5 page(s) / 189K

Publishing Venue

The IP.com Prior Art Database

Abstract

We propose a linear calibration method for optimizing power consumption of LO chain inside a frequency synthesizer (PLL), more specifically at oscillator (VCO) and high frequency (HF) divider level. Both voltage and frequency check loops are implemented in the VCO and Divider couple, ensuring their correct operation. Some specific blocks - such as calibration dividers and digital logic - are activated only during calibration phase, with no penalty on overall PLL current consumption. By using the proposed method, constant VCO output amplitude and an optimized VCO current consumption are obtained for each corner, temperature, supply voltage and each sample. Thanks to the frequency check loop, one can also guarantee correct division ratio (divider's chain), during the bias current optimization of the VCO.

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Calibration Method for Guaranteeing LO Chain

Functionality & Performance while Reducing Power Consumption

Abstract

We propose a linear calibration method for optimizing power consumption of LO chain inside a frequency synthesizer (PLL), more specifically at oscillator (VCO) and high frequency (HF) divider level. Both voltage and frequency check loops are implemented in the VCO and Divider couple, ensuring their correct operation. Some specific blocks - such as calibration dividers and digital logic - are activated only during calibration phase, with no penalty on overall PLL current consumption. By using the proposed method, constant VCO output amplitude and an optimized VCO current consumption are obtained for each corner, temperature, supply voltage and each sample. Thanks to the frequency check loop, one can also guarantee correct division ratio (divider's chain), during the bias current optimization of the VCO.

Introduction

In today’s portable applications, such as ZigBee, Bluetooth Low Energy, Wi-Fi or Automotive Radar, the overall power consumption plays an important role. Optimal performance, low power consumption together with embedded BIST (Built-in-Self-Test) functions allows achieving high competitive products, while reducing test time and facilitating integration in a single package. In a fully integrated transceiver, the frequency synthesizer (or PLL – Phase Locked Loop) is one of the key elements, often requiring high performance and high current drain. In such a context, efforts must be undertaken to reduce PLL overall power consumption, while keeping its correct operation. In a PLL, the oscillator (VCO or DCO or any other type), the high frequency (HF) dividers and HF buffers are the main elements, and a careful trade-off need to be done to optimize their performance while reducing their current consumption.  In a VCO design, bias current is often oversized to guarantee oscillation in all conditions, and much more current is burned than really needed for start-up and sustainability (oscillation condition). For HF dividers and HF buffers, bias current is again oversized during design phase to guarantee a correct frequency division and/or a minimum signal level needed to drive the following stage - generally placed far away from the buffers.

In order to fulfill all these requirements and to circumvent the bias current over sizing during VCO and dividers design, a solution is proposed, and comprises:

- a method that finds the bias current needed to fulfill both Start-up and Sustainability conditions for the VCO – VCO operates with essential current, regardless of process, temperature and supply voltage.

- a method which checks the divider’s output frequency during VCO bias calibration phase. The divided frequency in both up and down calibration phases are compared to ensure VCO and Divider arrangement works correctly. VCO amplitude level is enough to get a correct division, with no bias over sizing.

- a method and routin...