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A DFT direct method for testing 'power gate enable' logic of any power gating topology in an ASIC

IP.com Disclosure Number: IPCOM000235946D
Publication Date: 2014-Mar-31
Document File: 4 page(s) / 184K

Publishing Venue

The IP.com Prior Art Database

Abstract

Power gate structures in state of the art SoC designs have a high number of power switches and complex topologies for power gating enable signal distribution. The number of buffer logic gates used to route the enable signal is proportional to the number of power switches, which can be huge in number. This structure must be designed to enable the testability of manufacturing defects. Existing methods test the 'power gating structure’ as a whole. The methods check the logic level of ‘gated power supply’ to validate the correct functionality of the ‘power gating structure’. In some cases this approach fails to detect the fault, while others have many drawbacks for a practical circuit implementation like lot of silicon overhead and long testing durations. Moreover, no method exists for direct testing of manufacturing defects in the 'power gating enable (digital) logic circuit' of the 'power gating structure' in cases where the enable signal is distributed in a tree like structure with large number of diverging open ended branches. There is a need for a fast and reliable method of checking the power gate enable tree. In this paper we propose a method to detect manufacturing defects (stuck-at-faults) in the digital logic gates (buffer gates) used for the 'power gate enable' logic in a 'power gating switch structure'.

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A DFT direct method for testing 'power gate enable' logic of any power gating topology in an ASIC

Abstract

Power gate structures in state of the art SoC designs have a high number of power switches and complex topologies for power gating enable signal distribution. The number of buffer logic gates used to route the enable signal is proportional to the number of power switches, which can be huge in number. This structure must be designed to enable the testability of manufacturing defects.  Existing methods test the 'power gating structure’ as a whole. The methods check the logic level of ‘gated power supply’ to validate the correct functionality of the ‘power gating structure’. In some cases this approach fails to detect the fault, while others have many drawbacks for a practical circuit implementation like lot of silicon overhead and long testing durations. Moreover, no method exists for direct testing of manufacturing defects in the 'power gating enable (digital) logic circuit' of the 'power gating structure' in cases where the enable signal is distributed in a tree like structure with large number of diverging open ended branches.  There is a need for a fast and reliable method of checking the power gate enable tree. In this paper we propose a method to detect manufacturing defects (stuck-at-faults) in the digital logic gates (buffer gates) used for the 'power gate enable' logic in a 'power gating switch structure'.

Problem Description

The 'power gate MOS switch' in a typical 'power gating structure' is laid out in row/column segments. A 'power gate structure' may have of the order of a million 'power gate MOS switches'. Each 'power gate MOS switch' has a 'power gate enable'. The 'power gating enable logic circuit' mainly contains buffer and delay cells to distribute 'power gate enable' signal to all 'power gate MOS switches' in a 'power gating structure'. There are different topologies of 'power gate enable signal' distribution. A typical topology, as shown in Figure 1, could be where 'power gate MOS switches' are laid out in rows and the 'power gate enable' is distributed to the switches in a tree like structure. This structure will have divergent branches which are open-ended.

                As shown in Figure 1, the m branches of PG_EN_OUT are terminated open ended and thus not connected to any scan chain. In case of stuck-at fault in any of the leading buffers like B1, B2, B11, B21 etc, the whole ‘power gating structure’ fails. And in absence of any DFT logic, such gross failure may go undetected in a shipped part.

The existing DFT methods do not cover the direct testing of such structure. One of the methods checks the voltage level at VDD_GATED. In this method, if only a single or a few enable tree segments has faults, then it may go undetected as res...