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Robust and Efficient Standard Cell Power Connections using Rectangular Vias

IP.com Disclosure Number: IPCOM000235947D
Publication Date: 2014-Mar-31
Document File: 5 page(s) / 410K

Publishing Venue

The IP.com Prior Art Database

Abstract

In lower technology nodes (45nm and below), fabs are recommending maximum usage of rectangular vias over square vias. Power grid designers have started using rectangular vias for power stripe connections. In lower technology nodes (mainly 40nm and below) the standard cell power grid is predominantly based on NXT grid architecture that has both M1 and M2 horizontal power rails, with an array of square vias connecting them (for example 28nm ARM libraries). Using rectangular vias in the standard cell power grid puts constraints on standard cell placement. Hence the challenge is to use rectangular vias for standard cell power connection without any overhead. Our proposed power grid structure facilitates the maximum usage of rectangular vias for horizontal M1-M2 power rail connection without any overhead.

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Robust and Efficient Standard Cell Power Connections using Rectangular Vias

Abstract

In lower technology nodes (45nm and below), fabs are recommending maximum usage of rectangular vias over square vias. Power grid designers have started using rectangular vias for power stripe connections. In lower technology nodes (mainly 40nm and below) the standard cell power grid is predominantly based on NXT grid architecture that has both M1 and M2 horizontal power rails, with an array of square vias connecting them (for example 28nm ARM libraries). Using rectangular vias in the standard cell power grid puts constraints on standard cell placement. Hence the challenge is to use rectangular vias for standard cell power connection without any overhead. Our proposed power grid structure facilitates the maximum usage of rectangular vias for horizontal M1-M2 power rail connection without any overhead.

Problem Definition

With the advance technology nodes and shrinking metal/via geometries, meeting the IR drop requirements and improving the manufacturability has become very difficult. The use of rectangular vias has now become imperative for better manufacturability and IR drop.

Existing standard cell power grid layout (for example, 28nm ARM standard cells) uses the following structure to connect M1 and M2 power rails:

·                 Horizontal thin M1 power rail inside standard cell (referred to as Metal1 follow-pin).

·                 Horizontal M2 power rail inside standard cell, overlapping continuously with M1 (referred to as Metal2 follow-in).

·                 Array of square Via1 inside standard cell to connect these two overlapping power rails.

·                 The two adjacent via1 are kept at the pitch equal to width of placement grid to facilitate exact overlapping of power vias of one standard cell with the power vias of the standard cell over or below it (as shown in below snapshot).

 

This structure is not optimal in terms of manufacturability and IR drop as it does not deploy the usage of rectangular vias for M1 and M2 power rail connections.

If we try to use rectangular VIA1 inside current standard cell structure we end up with following problems:

Proposed Solution

We propose the following M1 – Via1 –M2 power grid structure:

·                    Horizontal thin M1 power rail as a part of standard cell design.

·                    Horizontal M2 power rail overlapping continuously with M1, but as a part of regular power grid outside standard cell.

·                    Array of rectangular Via1 present at minimum rectangular Via1 pitch as per DRM. This array is also a part of r...