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A Method For Efficient Runtime Estimation of Leakage Power by Firmware

IP.com Disclosure Number: IPCOM000236138D
Publication Date: 2014-Apr-08
Document File: 5 page(s) / 156K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method for efficient runtime estimation of leakage power by firmware using manufacture time and run time data is disclosed.

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This is the abbreviated version, containing approximately 42% of the total text.

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A Method For Efficient Runtime Estimation of Leakage Power by Firmware

Disclosed is a method for efficient runtime estimation of leakage power by firmware using manufacture time and run time data .


1. Introduction

The ability to efficiently breakdown total hardware power, while running an application or workload, into separable sub-components of power (leakage and dynamic power) enables accurate energy accounting of virtual machines, as shown in Figure 1. This also improves system level power management techniques for achieving higher chip frequencies and better Server Efficiency Rating Tool score.

Figure 1: Virtual machine energy charge back

The disclosed scheme provides a method of estimating leakage power of a microprocessor or microprocessor unit.

The following are steps of the disclosed method:

Determining a set of power gated domains (example: the domains currently turned on, or domains assigned to a virtual machine), for each power gated domain in the set.

Measuring operational temperature and voltage associated with the domain. Obtaining process, voltage, temperature (PVT)-independent parameter table (length/width/count) associated for the each transistor type that makes the domain. Obtaining the process corner dependent characteristics.

Calculating leakage power across each transistor type.

Summing the leakage power for each transistor type. The fraction of time (derating factor) a domain is powered on in the last interval is determined. The leakage power of the domain is multiplied by the derating factor to get a derated leakage power. The fraction of time is determined by using two counters. One counts the power-on cycles and one counts the total cycles.

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In the case of energy accounting for virtual machines, there are several scenarios where the processor core power cannot be measured directly, and hence must be estimated during runtime. Leakage power is estimated per core. This enables higher accuracy of energy accounting on processors which have per core voltage controls. In the case of accurate idle power for trade-off of chip leakage power with fan power, the disclosed method improves closed loop controller reaction time by accurately predicting the leakage power for a future temperature set-point.


2. Overview & Description

Figure 2 shows the four main steps of the disclosed method.

Figure 2: Overview of the method


2.1 Step 1: Generate accurate PVT-independent Leakage Abstract

For each design unit that makes up the hardware block (example: processor), generate a PVT-independent abstract. For example, the physical design units that make up a Processor.

For each physical unit, input the physical design netlist into PVT-independent leakage abstract generation tool. Examples of leakage power contributors are width, length, and count "accumulated" on a per device type basis, per voltage rail.


2.2 Step 2: Create leakage abstract for each power-gating domain

A leakage abstract for each power-gating domain i...