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Method and System for Background Execution of Latency Operations

IP.com Disclosure Number: IPCOM000236141D
Publication Date: 2014-Apr-08
Document File: 4 page(s) / 142K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system is disclosed for optimizing execution of one or more long latency operations in a pipelined processor without interfering with one or more other operations.

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Method and System for Background Execution of Latency Operations

In a pipeline processor, at any given time, one or more complicated instructions are being fetched, decoded and executed in different stages. The one or more complicated instructions are broken down into one or more "sub-programs" (millicode) that use multiple existing simpler instructions to perform complicated functions that the instructions are designed to perform. However, some operations require certain hardware action that spans across multiple cycles and cannot be implemented by a series of simpler instructions. The simpler instructions are typically implemented by assigning an execution unit to perform a required operation, while blocking other

instructions from being executed in the execution unit.

Such implementation of multi-cycle instructions can be wasteful as it disrupts execution of commands for extended periods of time, while main execution resources of the

execution unit are not utilized. Moreover, in a multi-threading environment, one thread that takes over an execution unit in this manner may be impacting not just its own execution but other threads' execution as well.

The following are a few examples of long latency operations:


• Read Special Pervasive Registers (RSPRs) are used for accessing various registers containing interrupt, instrumentation and other information and are distributed across different units within a processor. A Load-Store Unit (LSU) receives requests to access the RSPRs. If the register is located in the LSU, the LSU returns its content. Otherwise the LSU forwards read requests to other units that eventually return the requested data. While RSPRs requests are forwarded to other units, the LSU is unable to perform regular load and store accesses to storage.


• Perform Translator Operation (PXLO) - The LSU assists with performing different address translator operations, such as, but not limited to, testing translations of one or more virtual addresses and updating or purging one or more transaction tables. One or more translator operations are issued to the LSU which forwards a corresponding request to a translator unit. The one or more translator operations can span across many cycles, during which LSU is unable to execute regular storage accesses.

Disclosed is a method and system for optimizing execution of one or more long latency operations in a pipelined processor without interfering with flow of regular storage accesses.

In an embodiment, the method and system integrates a dedicated execution facility into the LSU. The dedicated execution facility executes the one or more long latency operations without interfering with flow of regular storage accesses. For example, when

the one or more long latency operations are initially issued to the LSU, the LSU allocates the dedicated execution facility for capturing one or more operation

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parameters associated with the one or more long latency operations. The LSU...