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Diagnosis System and Method for ROM Failure

IP.com Disclosure Number: IPCOM000236216D
Publication Date: 2014-Apr-11
Document File: 5 page(s) / 350K

Publishing Venue

The IP.com Prior Art Database

Abstract

In current IC products, the ROM array is merged with other IPs to achieve some special applications, which may be used to store critical data and code. ROM tests are run to check the integrity of the ROM data/code. It’s necessary to diagnose failures if the ROM test fails in order to reduce yield loss. Thus, it’s important to have an effective method and apparatus to diagnose ROM test failures.

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      Diagnosis System and Method for ROM Failure

Abstract:

       In current IC products, the ROM array is merged with other IPs to achieve some special applications, which may be used to store critical data and code. ROM tests are run to check the integrity of the ROM data/code.  It’s necessary to diagnose failures if the ROM test fails in order to reduce yield loss.  Thus, it’s important to have an effective method and apparatus to diagnose ROM test failures.

1.   Background

           

With the development of semiconductor technology and design requirement, ROM array may be used to store critical data/code for some special application cases. But the array may be vulnerable to defects due to its high density and complex structure and thus may be a sore of yield loss. In current practice, ROMBIST is widely used for ROM test, in which ROM data is read out and compressed to a signature, the signature is then compared to a golden signature to determine whether ROM test passes or fails.  ROMBIST however does not provide failure diagnosis information indicating the source and the type of the fault.  Thus it is difficult to do ROM failure diagnosis once the ROM array is defective.  In some conventional methods, either complex algorithms (e.g., probabilistic algorithms), complex circuits (partition array to small partitions and use signatures of different partition groups to analyze the source of the fault), and or manual analysis are used for ROM failure diagnosis.  These methods are not cost-effective or accurate.

In this article, an effective method and apparatus is offered to run ROM failure diagnosis, so TE/DE/AE /customers can identify the failure location or failed data directly and quickly without the need for complex circuits or complex algorithms. Also the method and apparatus can be used to test a ROM array so it’s possible to remove ROM BIST engine and save die size.

2.   Proposed diagnosis system for ROM failure

Normally in IC design, RAM array and external interface are implemented as basic functions for customers;  the external interface can be JTAG/SWD, or other communication interface.  It’s possible to use the RAM array and its interface in ROM failure diagnosis system.  The external interface is used to write gold ROM data/code to RAM, and configuration information to registers, then read back diagnosing results so that users can take next step, such as yield improvement.  The detailed design diagram is shown in Figure 1. The main components besides RAM and external interface are listed below:

 

  1. Debug control unit to control debug flow and save test and debug status;
  2. Memory read and compare control unit: to generate memory read address and corresponding  control signals, and compare the data from RAM and ROM;
  3. Some MUX logic to select valid write/read signals to RAM and ROM;
  4. Some other IPs needed, such as MBIST engine for RAM or ROM.

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