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Programmable PCI-Express Root Port Bifurcation

IP.com Disclosure Number: IPCOM000236239D
Publication Date: 2014-Apr-14
Document File: 4 page(s) / 110K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is an apparatus and method to enable firmware or software in a host system to detect the number of PCI-Express (PCIE) devices or links on a PCIE add-in card and to program the configuration of PHBs and PCIE lanes of a root complex connecting that add-in card slot according to the requirements of the add-in card type.

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Programmable PCI -

Disclosed is an apparatus and method to enable firmware or software in a host system to detect the number of PCI-Express (PCIE) devices or links on a PCIE add-in card and to program the configuration of PHBs and PCIE lanes of a root complex connecting that add-in card slot according to the requirements of the add-in card type.

    A PCIE root complex commonly incorporates a plurality of PHBs and a plurality of PCIE lanes to form one, or a plurality of, PCIE links emanating from the root complex chip. The PCIE links connect to PCIE devices or add-in slots on a system motherboard. Additionally, a particular PCIE add-in card slot on a system motherboard may provide a plurality of PCIE links to connect to a plurality of PCIE devices on a single add-in card. Various add-in card types may then utilize that slot, each having from one to as many PCIE devices as there are PCIE links connected to that add-in card slot and having varying PCIE link widths to devices on that card.

    A PCIE add-in card may be alternatively utilized to pass-through PCIE links from PHBs within a root complex to cables that connect, in turn, to PCIE devices or add-in card slots in a PCIE IO expansion enclosure. Such an add-in card may provide a single PCIE link conveyed across the cables to a single PCIE device or add-in card slot in the IO expansion enclosure or may provide a plurality of PCIE links conveyed independently across individual cables to a plurality of PCIE devices or add-in card slots within the IO expansion enclosure.

    Figure 1 illustrates an exemplary system motherboard application of root complex chips each having 3 PHBs in various combinations of PCIE links connecting to PCIE devices and add-in card slots on that motherboard and including an exemplary PCIE cable card plugged into a PCIE slot. Commonly, a root complex chip provides a particular number of PCIE lanes -- such as 16, 24, or 32 -- that may be associated with the PHBs within it. The number of PCIE lanes that the root complex chip provides is commonly limited by the number of pins available on the root complex chip. Ideally, a root complex chip is capable of distributing the PCIE lanes in variable combinations between the PHBs within it to enable application of that same root complex chip with motherboards of differing design or with differing PCIE device and add-in card slot configurations on a particular motherboard as illustrated in Figure 1.

    Typically, the motherboard design predetermines the number and width of PCIE links to devices or add-in card slots on that motherboard. In such applications, it is typical to utilize "strapping" pins input to the root complex chip from the motherboard or received from add-in card slots on the motherboard. The strapping pins may include device-present or other signals from an add-in card slot to indicate the number of devices or pass-through cables provided on the add-in card. At system power-on, the root complex senses the strapping...