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A Method and System for Allowing Simultaneous Access by Short Length Packets to a Direct Memory Access Engine

IP.com Disclosure Number: IPCOM000236269D
Publication Date: 2014-Apr-16
Document File: 2 page(s) / 30K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system is disclosed for allowing multiple requesters sending short length packets to simultaneously access a Direct Memory Access (DMA) engine by providing a Memory Mapped Input/ Output interface(MMIO) for handling the short length packets.

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A Method and System for Allowing Simultaneous Access by Short Length Packets to a Direct Memory Access Engine

Currently, crypto-symmetric key engines are configured to receive input from Direct Memory Access (DMA) operations. A requestor needing to perform an operation using

a crypto-symmetric key engine is required to first submit a request to a DMA engine for returning DMA operations. The request to the DMA engine can be submitted in the form of a packet. In cases where the packet is of short length such as, but not limited to, less than 256 bytes, a significant amount of time can be spent in building and subsequently executing, a packet for the request.

A potential solution for preferentially treating short length packets could be to build and

use a dedicated DMA channel, wherein the dedicated DMA channel is assigned a

higher priority than other DMA channels. Another potential solution could be to allow

the requestor to access the DMA engine via another path such as, but not limited to, a Memory Mapped Input/ Output interface (MMIO) path.

Disclosed is a method and system for allowing multiple requesters sending short length packets to simultaneously access a DMA engine by providing a MMIO interface for handling the short length packets. For example, the number of multiple requesters simultaneously accessing the DMA engine can be 16. The DMA engine can further be coupled to one or more input ports of one or more crypto symmetric key engines for providing input to the one or more crypto symmetric key engines. The method and system separates input and output areas of the DMA engine by provisioning multiple MMIO interface areas on the MMIO interface. Further each MMIO interface area maps onto a single low latency port on the DMA engine.

The method and system uses a set of buffers accessible by the MMIO interface for storing short length packets received from the multiple reques...