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Method for Providing Low-Latency Bus-Invert Coding for Pipeline Outputs

IP.com Disclosure Number: IPCOM000236289D
Publication Date: 2014-Apr-17
Document File: 3 page(s) / 103K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method is disclosed for providing low-latency bus-invert coding by combining an analog way to perform fast majority voting for one or more digital bits and a self-timed/asynchronous way to encode the one or more digital bits using the low latency bus-invert coding scheme.

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-Invert Coding for Pipeline Outputs

Invert Coding for Pipeline Outputs

Switching activity on on-chip wide data buses can consume a significant amount of processor power. There are known techniques to reduce the switching needed to transmit data such as bus-invert coding. Prior-art implementations of bus-invert coding add a large delay to the signal path and do not provide latched outputs . Hence the bus-invert coding technique takes a large amount of an existing clock cycle or requires adding a cycle to a data pipeline.

Disclosed is a method for providing a low-latency bus-invert coding, by combining two techniques namely:


1. An analog way to perform fast majority voting for one or more digital bits and

2. A self-timed/asynchronous way to encode the one or more digital bits using the low latency bus-invert coding scheme.

The fast majority voting is required for very small latency and without needing an extra clock cycle. On the other hand, the bus-invert coding utilizes asynchronous data clocking.

FIG. 1 is an exemplary circuit illustrating the low-latency bus-invert coding in accordance with the first technique described above.

-Latency Bus

Latency Bus -

Method for Providing Low -

Figure 1

A portion of the exemplary circuit illustrated in FIG. 1 implements the fast majority voting using a low latency latch and the circuit provides a stable output . If the data bits change after the clock, the final (encoded) output does not change. This means that no additional...