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Method and apparatus for detection and correction of duty cycle and quadrature phase errors in high frequency clocks

IP.com Disclosure Number: IPCOM000236341D
Publication Date: 2014-Apr-21
Document File: 6 page(s) / 149K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a power and area efficient technique for generating accurate clock phases. The technique uses a digital quadrature phase error correction circuit that converts I/Q timing differences to 25% duty-cycle pulses, which can be low-pass filters and compared to detect quadrature phase mismatch.

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Page 01 of 6

Method and apparatus for detection and correction of duty cycle and quadrature phase errors in high frequency clocks

Quadrature (or I/Q) clocks are commonly found in many mixed-signal circuits. However, mismatch in the clock generation or distribution (e.g., mismatch from devices or wiring parasitics) can lead to I/Q phase imbalance. In turn, this imbalance can result in a number of system-level errors depending on the application. Radio Frequency (RF) receivers can suffer from I/Q gain error as a result. Quadrature phase error in a

wireline transmitter results in duty-cycle distortion in the output data. Therefore, clock phase correction is a critical design requirement in all cases utilizing quadrature clocks .

The novel contribution is a digital quadrature phase error correction circuit that converts I/Q timing differences to 25% duty-cycle pulses. These pulses can be low-pass filters and compared to detect quadrature phase mismatch . This solution is compatible with existing DCC techniques and can be controlled through digital techniques , resulting in a power and area efficient technique for generating accurate clock phases .

The first embodiment of the invented approach is shown in Figure 1. The scheme consists of sensors and actuators to control both duty cycle errors and quadrature phase errors in a clock distribution network. The clock distribution network can be implemented in either Complementary Metal Oxide Semiconductor (CMOS) or current-mode logic. Rise and fall times of the CMOS clocks are adjusted to correct for duty cycle errors, while delays in the in-phase (I) and quadrature-phase (Q) paths are adjusted to correct for quadrature phase errors. Duty cycle correction (DCC) can be implemented using existing techniques. For example, the true and compliment I phases can be low-pass filtered to obtain a DC average, and then compared to ensure both true and compliment have equal DC average. This assumes that the edges of the true and compliment I phases are aligned, which can be ensured by inserting weak cross-coupled inverters at various points in the clock distribution network as seen in Figure 2. Logic finite state machines (FSM) can detect the point when both clocks have the same DC average using simple counter circuits. Rise and fall times can be adjusted using many known techniques; for example, controlling the current in current-starved inverters through the use the digitally-controlled current digital-to-analog converters (DACs), two sets of DCC/QCC circuits, and the duty-cycle detection circuit

with an I/Q phase error detection circuit. The same detection and correction technique can be applied for DCC on the Q-phase.

Figure 1: The first embodiment of the DCC/QCC circuit

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Page 02 of 6

After the calibration of the duty cycle, the I/Q quadrature phase error correction (QCC) for the first embodiment can be achieved using the circuit in Figure 2. I-to-Q separation can be measured through the following process: I...