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Method and System for Screening of Semiconductor Chips using Thermal Photon Detection

IP.com Disclosure Number: IPCOM000236378D
Publication Date: 2014-Apr-23
Document File: 3 page(s) / 44K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system is disclosed for screening of semiconductor chips using thermal photon detection.

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This is the abbreviated version, containing approximately 52% of the total text.

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Method and System for Screening of Semiconductor Chips using Thermal Photon Detection

Disclosed is a method and system for screening of semiconductor chips using thermal photon detection. The method and system detects incipient reliability faults and undetected electrical circuit faults of semiconductor chips. Incipient reliability faults can be such as, but not limited to, short circuit failures and open faults with high electrical field magnitude. Short circuit failure causes a circuit capable of evolving over time to cause the short itself to become open which localizes heating that damages adjacent circuitry. The open type fault expresses a high electrical field that evolves over time, for instance by the mechanism of electro-migration, to cause a short, a localized breakdown or current tunnelling.

In accordance with the method and system, semiconductor chips are screened as part of normal manufacturing test at wafer test or module test, by detection of high current (thermal photons) and optical photon emission from circuit defects. The screening can be applied at uncapped module test or wafer level test. Thereafter, the method and system acquires one or more high resolution thermal photon images and compares the images to known good thermal images. Image location is pre-calculated to observe regions of the device which were made redundant by repair operations and/or regions where untested potential faults exist. Images for reference and defect detection are acquired at maximum resolution for areas defined by logical-physical pre-calculation. Image acquisition (a sequence of images) is along an optimized a tool path.

The method and system enumerates the area of a redundancy or potential untested fault as chip geographic locations and produces an efficient tool path for detector image acquisition. Multiple tool paths are created for differing magnification selections, fault location probabilities are calculated using...