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Automated complier based microprocessor noise minimization means

IP.com Disclosure Number: IPCOM000236386D
Publication Date: 2014-Apr-23
Document File: 3 page(s) / 38K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method, applied to complier-based microprocessors, which determines whether changes can be made to chip operations controlled by the compiler in order to reduce di/dt (noise), while maintaining high performance to the many application metrics that the compiler team traditionally optimizes.

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Automated complier based microprocessor noise minimization means

Traditionally, microprocessor and complex server chip design teams work closely with a compiler team, with the compiler's goal being to get the most performance out of a given microprocessor's micro-architecture when running higher level programs and applications.

The compiler team generally uses a performance model (usually written in C or C++) that is written to closely match the low level function of the microprocessor. During the detailed design and implementation phase of a new microprocessor, the team that writes the performance model runs simulations of the model against various performance metrics, which help flush out performance bottlenecks in the processor design.

Once this performance model is tuned to very closely match the final functionality of the microprocessor, the compiler team continues to optimize the compiler software to provide the best performance when running the critical applications, which that microprocessor must support. The overarching goal of the compiler team is to always maximize performance for any given application.

In recent years, minimizing overall chip power dissipation while maintaining chip performance has become critical for customers and most applications. In response, chip teams have introduced additional architecture features that "throttle" performance to make sure power dissipation does not exceed defined limits. The chip performance model, and compiler, must be able to account for and model these features.

The background for the novel idea is that to reduce chip power and continue shrinking silicon/Complementary Metal Oxide Semiconductor (CMOS) process technology from 32nm to 22nm, and beyond to14nm, chip supply voltages must be reduced, and now run well below 1V, even down to 0.6-0.7V.

At the same time, complex analog functions such as Phase Locked Loops (PLLs) and Serializer/Deserializer (SerDes) high-speed Input/Output (I/O) are being integrated onto microprocessors to support increased clock frequencies, and much higher memory and I/O bandwidths to get data on and off chip efficiently. This analog circuitr...