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Method and System for Performing a High Yield, Low Cost and Scalable Three Dimensional Integration based on Double or Deep Buried Oxide Silicon on Insulator Structures

IP.com Disclosure Number: IPCOM000236391D
Publication Date: 2014-Apr-24
Document File: 5 page(s) / 119K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system is disclosed for performing a high yield, low cost and scalable three dimensional integration based on double or deep Buried Oxide Silicon on Insulator Structures.

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Method and System for Performing a High Yield ,

,

Low Cost and Scalable Three

Low Cost and Scalable Three

Dimensional Integration based on Double or Deep Buried Oxide Silicon on Insulator Structures
Disclosed is a method and system for performing a high yield, low cost and scalable three dimensional integration based on double or deep Buried Oxide (BOX) Silicon on Insulator (SOI) Structures.

Initially, a double BOX SOI for top wafer is utilized as illustrated in fig .1.

Figure 1

As shown in fig.1, the bottom layer is a silicon (Si) substrate, the layer above the Si substrate is a first BOX layer. Further, the layer on top of the BOX layer is also a Si layer with a thickness of several microns and a layer on top of the Si layer is a second BOX layer.

Thereafter, a Front End of Line (FEOL) or Back End of Line (BEOL) process is performed on the structure as illustrated in fig.2.

Figure 2

As shown in fig. 2, the blue layer on top of the BOX layer represents the BEOL process . Fig. 3 illustrates the next step of creating vias in the structure using lithography or

1


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Reactive Ion Etching (RIE).

As shown in fig.3, a Through Silicon Via (TSV) lithography is performed and RIE is performed uniformly till bottom of the first (thick) BOX layer. Here, the TSV is scaled down to submicron level based on wafer thickness to preserve device stress and TSV density is scaled up based on wafer to wafer alignment .

In the next step, a BEOL oxide is deposited and a Copper (Cu) plating is performed on the structure due to low aspect ratio of the TSV as sh...