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System For Reducing Incorrect Store Forwarding Due To Aliasing

IP.com Disclosure Number: IPCOM000236416D
Publication Date: 2014-Apr-24
Document File: 3 page(s) / 89K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to use a set of registers in a high-performance processor to hold instruction identifiers for load instructions that have experienced incorrect store forwarding due to address aliasing. This allows an aliasing load to finish successfully without penalizing other loads that overlap in absolute storage and still allows maximum processor frequency.

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System For Reducing Incorrect Store Forwarding Due To Aliasing

In high performance and especially out-of-order processors, operand store compare hazards significantly contribute to delays in instruction processing and checkpointing. One way to alleviate these delays is to speculatively forward data from stores to subsequent dependent loads. This forwarding is usually enabled by comparing a subset of a load's virtual address range to older stores' virtual address ranges. Since only a subset of the virtual address is used and the absolute address is not used, this approach suffers from the possibility of incorrect forwarding due to address aliasing.

Address aliasing occurs when the compared subset of the virtual address matches but

the full absolute address does not match. When this occurs, the load must be rejected and re-executed due to receiving incorrect data from a store instruction that does not overlap in absolute storage.

To prevent this situation from occurring repeatedly, the store may be disabled from forwarding altogether. This penalizes other loads that actually overlap the store in absolute storage due to no longer being able to receive forwarded data.

Another existing solution is to hash additional address bits into the address compare to

reduce aliasing, but this method can increase the depth of the logic and reduce processor frequency.

A solution is required that allows an aliasing load to finish successfully without

penalizing other loads that overlap in absolute storage and still allows maximum processor frequency.

The novel solution is a method to use a set of registers to hold instruction identifiers for load instructions that have experienced incorrect store forwarding due to address aliasing. Upon detection of a reject due t...