Browse Prior Art Database

Smart way to save power (leakage and dynamic) consumption by removing power/ground connections of unused logic

IP.com Disclosure Number: IPCOM000236421D
Publication Date: 2014-Apr-24
Document File: 5 page(s) / 1M

Publishing Venue

The IP.com Prior Art Database

Abstract

All SOCs have lot of un-used digital logic which does not serve any functional purpose, e.g. a logical gate with none of the output driving anything. This unused logic consumes static or dynamic or both static and dynamic power. This paper presents a novel approach to save this static and dynamic power of unused logic by disconnecting the power ground connections of standard cells without any overhead on the design.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 56% of the total text.

Smart way to save power (leakage and dynamic) consumption by removing power/ground connections of unused logic

Abstract

All SOCs have lot of un-used digital logic which does not serve any functional purpose, e.g. a logical gate with none of the output driving anything. This unused logic consumes static or dynamic or both static and dynamic power. This paper presents a novel approach to save this static and dynamic power of unused logic by disconnecting the power ground connections of standard cells without any overhead on the design.

Problem Definition

Power saving has become imperative in lower technology nodes. Achieving the power numbers has become very difficult with conventional power saving techniques. All the SOCs have lot of un-used digital logic which does not serve any functional purpose but consume both dynamic and static power. This unused logic can be because of following reasons:

•      Restricting tool algorithms by user specified pragma’s/attributes to deliberately prevent certain logic from getting optimized/removed e.g. Don’t-touch attributes.

•      Preventing boundary optimization on certain designs e.g. DFT logic, fuse map logic etc.

•      Using third party IP/New IP where aggressive logic optimization is deliberately restricted for the ease of future ECOs.

•      Hierarchical implementation preventing certain unused logic across hierarchical interface from getting optimized.

•      Inefficiency of EDA tool to optimize/remove un-used digital logic.

•      Unused logic left after implementing ECO.

•      Spare cel...