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High stand-off IC for two layer IC on PCB

IP.com Disclosure Number: IPCOM000236445D
Publication Date: 2014-Apr-25
Document File: 2 page(s) / 364K

Publishing Venue

The IP.com Prior Art Database

Abstract

Current PCBs can only have one layer of ICs attached on the board surface. In this paper, we propose a method for providing two layers of ICs on a PCB surface.

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High stand-off IC for two layer IC on PCB

Abstract: 

Current PCBs can only have one layer of ICs attached on the board surface.  In this paper, we propose a method for providing two layers of ICs on a PCB surface.

Body:   

Printed Circuit Board (PCB) space is critical for some devices, such as for sensors and entertainment devices.  We propose saving PCB space, or even shrinking the PCB, by allowing for chips to be stacked on the PCB.  Integrated Circuits (IC) are becoming thinner and thinner.  In current conventional PCB layout, all of the ICs are placed side by side.  Thus, there are areas of the board, such as underneath some of the ICs, are effectively exploited, especially the area under large ICs. 

We propose placing smaller components such as capacitors, resistors, small QFNs or BGAs, and all passive components under those big ICs by making the larger ICs with a high stand-off.  The drawings below illustrate a high stand-off IC with a lower stand-off IC located directly beneath the high stand-off IC.   

For example, current JEDEC specifications provide an IC having a standoff of about 0.1mm (e.g., JEDEC SPEC: SOIC stand-off: 0-0.1mm, QFP: 0.05-0.15mm).  We propose a high stand-off IC with a stand-off of 1-5mm or higher, depending on the first layer components height.

The current Surface Mount Technology (SMT) process is:

Screen  ---- Mount all components ----- reflow --- AOI.

A new SMT process flow for high stand-off ICs would be:

 

Screen  ---- Mount...