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Method and Apparatus for Pin Remapping Verification in SoC

IP.com Disclosure Number: IPCOM000236447D
Publication Date: 2014-Apr-25
Document File: 5 page(s) / 123K

Publishing Venue

The IP.com Prior Art Database

Abstract

Pin remapping is commonly used in current design to highly reduce the pin numbers of a chip. At the same time, how to verify mountains of pin remapping in a SoC (System on Chip) is a hot topic, and also a big challenge. This paper first introduces current verification flow of pin remapping and the bottlenecks of the flow, and then raises a new automatic method, which can highly improve the efficiency of verification, at the same time, achieves high verification completeness by avoiding verification holes.

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Method and Apparatus for Pin Remapping Verification in SoC

Introduction

Pin remapping is commonly used in current design to highly reduce the pin numbers of a chip.  At the same time, how to verify mountains of pin remapping in a SoC (System on Chip) is a hot topic, and also a big challenge. This paper first introduces current verification flow of pin remapping and the bottlenecks of the flow, and then raises a new automatic method, which can highly improve the efficiency of verification, at the same time,  achieves high verification completeness by avoiding verification holes.  

Current Flow and its bottlenecks

Figure 1: Current Verification flow for pin remapping

Figure 1 shows the current verification flow for pin remapping. From the figure, we can see that with this flow, these issues are met (taking iic as an example):

·                                                                                   The connection between SoC and VIPs is fixed (pta0/pta1 connects one VIP, ptc6/ptc7 connects one VIP), which means that verification engineer can never verify ptc6/pta0 and ptc7/pta1, so testcases can only cover part of the pin remapping design because of the fixed testbench connection.

·                                                                                   To a different SoC, the pinout can change significantly. To meet the design, the testbench should be updated manually. In some extreme situations, this part of work is really hard due to a) a huge number of pin remapping and b) the pins do not always make couples.  For example, using iic as an example, the numbers of SCL and SDA are not the same in some SoC, so to avoid multiple connection, some dummy tb_pad are needed.

·                                                                                   In a testbench, the C code should co-work with the v/sv, so the complicated testbench connection needs complicated C codes. This makes some common C code be with low reusability.

·                                                                                   Multiple VIPs are instanced for one IP in the testbench, so multiple TRIGGERs/MAILBOXs are needed to define for each instanced VIP being used. And also makes the testbench very large.

To meet the requirements in current verification flow, a new method has been developed:

·                                                                                   Improve the reusability of the testbench, including both v/sv files and C files.

·                                                                                   Flexible testbench connection which user can control in the C testcase is needed.

·                                                                                   The pin remapping design is from the pinout, is there a way to generate this part of testbench automatically?  If yes, the verification progress can pull-in a lot. And also makes sure that the verification and design are from the same source that is the system pinout.

·                                                                                   One VIP is instanced for one IP, making the testbench  compact saving other resources, such as mailbox, trigger, etc.

New High-efficiency Method

Figure 2: New Verification Method for Pin remapping

Figure 2 shows a new verification method for pin remapping that includes the following key components and benefits:

Multiplexers: Used to select a speci...