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A Batch Process for Creating Vicinal Surface on Multiple SiC Wafers and Producing Single Graphene without Pitting the Surface

IP.com Disclosure Number: IPCOM000236467D
Publication Date: 2014-Apr-29
Document File: 3 page(s) / 133K

Publishing Venue

The IP.com Prior Art Database

Abstract

A batch process is disclosed for creating vicinal surface on multiple Silicon carbide (SiC) wafers and producing single graphene without pitting the surface.

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A Batch Process for Creating Vicinal Surface on Multiple SiC Wafers and Producing Single Graphene without Pitting the Surface

Disclosed is a batch process for creating vicinal surface on multiple Silicon carbide (SiC) wafers and producing single graphene without pitting the surface .

When a Silicon Carbide (SiC) wafer comprising scratches and roughness has silicon (Si) islands deposited on it, and is covered with another SiC wafer and annealed in vacuum at 14500 C for a few minutes under Argon (Ar) or any other inert gas flow, then a single layer or few layers of graphene grow epitaxially on a vicinalized SiC surface.

If the bottom wafer of a two wafer stack can be graphitized , then two wafers of a three

wafer stack can also be graphitized, where the second wafer from the bottom acts as the cap for the first wafer from the bottom . Here, the third wafer from the bottom acts as the cap for the second wafer from the bottom .

From the stack of the three wafers, the bottom two wafers include vicinalized and graphitized surfaces but not pitted surfaces. Further, the bottom two wafers comprise a single layer or few layers of graphene grown epitaxially on the vicinalized SiC surface. Both vicinalization and graphitization are combined into a single step and performed concurrently for both the wafers. The top wafer which is third from bottom is reused as a top cap wafer for another vicinalization or graphitization batch process .

In addition, the stack of three wafers is increased to a stack of five wafers or a stack of n wafers, wherein n corresponds to a number of wafers that is limited by size of an annealing tool hot zone. Further, the number of wafers depends on structural stability of such a stack during processing and transferring into and out of a processing chamber.

Initially, Si islands of appropriate size and area density are deposited on several SiC

wafers in the batch process. In a preferred scenario, such a process is performed in a high temperature Ultra High Vacuum...