Browse Prior Art Database

Method and System for Providing an Independent Multi Gate Controlled FinFET Transistor

IP.com Disclosure Number: IPCOM000236470D
Publication Date: 2014-Apr-29
Document File: 5 page(s) / 93K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system is disclosed for providing an independent multi gate controlled Fin Field-Effect Transistor (FinFET) transistor. The method and system includes three independent gates controlled FinFET Device fabricated by standard FinFET Replacement Metal Gate (RMG) process.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 87% of the total text.

Page 01 of 5

Method and System for Providing an Independent Multi Gate Controlled FinFET Transistor

Disclosed is a method and system for providing an independent multi gate controlled Fin Field-Effect Transistor (FinFET) transistor. The method and system includes three independent gates controlled FinFET Device fabricated by standard FinFET Replacement Metal Gate (RMG) process.

In accordance with the method and system, a ring shaped mandrel is used to form a Fin layout that has space for gate landing in between two fins as illustrated in Fig. 1.

Figure 1

Thereafter, a dummy poly gate is formed wherein the dummy poly gate has a dummy gate oxide underneath as illustrated in Fig. 2.

1


Page 02 of 5

Figure 2

This assists in forming a spacer, source/drain, middle of line (MOL) dielectric using standard CMOS flow as illustrated in Fig. 3. The source/drain may include epitaxy to lower source/drain resistance.

2


Page 03 of 5

Figure 3

Thereafter, the dummy poly gate is etched out by using ammonia etching as illustrated in Fig. 4.

Figure 4

3


Page 04 of 5

The removal of dummy poly gate assists in forming a high K metal gate as illustrated in Fig. 5.

Figure 5

Thereafter, Reactive Ion Etching (RIE) is performed until Fin is revealed. This results in polishing down to reveal three gates as illustrated in Fig. 6. Each gate may have different gate bias depending on configuration of a circuit.

4


Page 05 of 5

Figure 6

Thus, the method and system disclosed herein provides three independent gate...