Embedded Dynamic Random Access Memory Circuit with Extra Bit-line for Storing Read Only Memory Data
Publication Date: 2014-May-02
The IP.com Prior Art Database
An embedded Dynamic Random Access Memory (eDRAM) circuit is disclosed for storing Read Only Memory (ROM) data by employing one extra bit-line in the eDRAM circuit.
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Embedded Dynamic Random Access Memory Circuit with Extra Bit - Read Only Memory Data
Embedding Read Only memory (ROM) data into on-chip memory such as Static Random Access Memory (SRAM) has been suggested for long time. If ROM data can be inserted into on-chip memory without leading to an area increase in bit-cells, large ROM data can be used without much overhead in the system , and such ROM data can be used as accelerators for fast math function evaluation , on-chip logic test, and so on.
Previously proposed ideas have tried to embed ROM data in SRAM cells . An embedded Dynamic Random Access Memory (eDRAM) can be designed to store RAM data only. The eDRAM can be used to store additional ROM data with an extra bit -line. Depending on the ROM data, each eDRAM cell can be connected to one of two bit-lines.
During RAM mode operations, both bit-lines are driven and sensed such that RAM mode operations are the same as that of conventional operations . During ROM mode operations, RAM data is copied into a buffer (one buffer per one eDRAM sub-array), then one bit-line is driven by '0' (ground signal), pre-charged to supply voltage, and then sensed by a sense amplifier. That way, connection of bit-line to eDRAM cell can be detected. Therefore, via connection which connects the eDRAM cell to one of two bit-lines becomes physical ROM data. After the ROM mode operations, buffer data is copied back into eDRAM, and hence the RAM data is not affected by ROM mode operations.
Conventional eDRAM bit-cell consists of one access transistor and one capacitor . By charging and discharging a capacitor, logic data of '0' or '1' can be stored.
Fig. 1 shows conventional eDRAM bit-cells and peripheral circuits illustrating the bit-cells which are connected to one common bit-line such as BL shown in Fig. 1. For read operations, bit-lines are pre-charged, while word line WL is turned-off, and then WL is turned-on. Voltage sensing through a sense amplifier (SA) can produce read output which is the voltage level that is stored in a capacitor.
-line for Storing
line for Storing