Six-Transistor Static Random Access Memory with Extra Word-line for Embedding Read Only Memory Data
Publication Date: 2014-May-02
The IP.com Prior Art Database
Disclosed is a six-transistor (6T) Static Random Access Memory (SRAM) circuit with extra word-line for embedding Read Only Memory (ROM) data.
Page 01 of 2
Six- Read Only Memory Data
There have been lots of efforts to embed Read Only Memory (ROM) features into Static Random Access Memory (SRAM). The SRAM employs one extra word-line and one of two word-lines is selectively connected to access transistors of SRAM bit-cells. This can be used to obtain ROM data density which is as large as RAM data density . However, ROM operations go through complex steps, such as copying RAM data into a buffer, write '1's, write '0', and copying back RAM data from the buffer . Hence, ROM mode operations have high latency. Moreover, five-transistor (5T) SRAM operations (which are required during ROM mode operation) are not as stable as six-transistor (6T) operations. Hence, stable and fast ROM operations are required.
Disclosed is a 6T SRAM circuit with an extra word-line for embedding ROM data. Here, ROM data is determined by via positions, wherein one of two word-lines is connected to access transistors. However, every other bit-cell is ignored when considering ROM data such that ROM data read operations are very simple and fast .
Fig. 1 illustrates an exemplary design of the 6T SRAM circuit.
In Fig. 1, assume that cell 0 has ROM data '0' and cell '2' has ROM data '1'. Further, assume that cell 1 and every other odd-number cells do not contain ROM data.
Accordingly, as shown, ROM data 0 in cell 0 leads to connections to WL0 for AXL and
AXR (access transistors). Similarly, ROM data 1 in cell 2 leads to connections to WL1 for AXL and AXR. Further, cell 1 and every odd-number cells follow connectivity or