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Software-Friendly Underrun/Overrun Processing in Audio Data Transfer Peripherals

IP.com Disclosure Number: IPCOM000236563D
Publication Date: 2014-May-02
Document File: 6 page(s) / 672K

Publishing Venue

The IP.com Prior Art Database

Abstract

Data buffer under-run and over-run occur from time to time in data transfer peripherals and may result in unbearable listening experiences, such as channel swap. Also time-alignment between different audio / video streams are corrupted due to this problem. In this article, a simple data buffer under-run and over-run scheme is proposed to handle this problem. The scheme allows for much simpler time alignment.

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Software-Friendly Underrun/Overrun Processing in Audio Data Transfer Peripherals

Abstract

Data buffer under-run and over-run occur from time to time in data transfer peripherals and may result in unbearable listening experiences, such as channel swap.  Also time-alignment between different audio / video streams are corrupted due to this problem.  In this article, a simple data buffer under-run and over-run scheme is proposed to handle this problem.  The scheme allows for much simpler time alignment.

Problem Description

In audio peripherals, there are always flowing structured data. That means, the data have some structure: adjacent data are aiming at different audio channel.  For example, Fig. 1 shows the I2S protocol, where SCK means the serial transmitting clock, WS mean word select, and SD means the serial audio data. WS low denotes transmitting left channel, and WS high denotes transmitting right channel.

Fig. 1 I2S protocal

In general system, the data are bulky, and they cannot be stored inside the peripheral itself. So either DMA or the CPU core has to do the data transfer. At the same time, at the chip interface, the data is flowing constantly in a definite speed. So the DMA or the CPU has to transfer enough data from / to the peripherals at the same average rate as the physical interface requires.

An example system is shown in Fig 2.

Fig. 2 Audio System

Inside the chip, due to system design constraints, and possibly instant bandwidth shortage, the input data may not be fetched in time from the receiver buffer (which is called overrun), or the output data may not be available in time to the transmitter buffer (which is called underrun).

When the data are flowing into or out of the chip, it has a structure embedded in the data frame, at the chip’s physical interface, as shown in Fig 1.

While the data are stored and transferred inside the chip, only logical structure remains. For example, the 1st sample from/to RAM is for left channel, and the 2nd sample from/to RAM is for the right channel.

When overrun or underrun happens, the logic structure in general has lost sync with the physical interface. If not handled correctly, channel swap will be heard, and this is more annoying than simple time delay.

Fig 3 is an example of transmit channel swap.

In Fig. 3, ESAI is the audio peripheral which implements I2S protocol, Frame sync high means Left channel to be transmitted, and Frame sync low means right channel to be transmitted.  Rn and Ln denote the nth sample of the right channel and the left channel.

The 1st and 2nd frame sync is correctly synchronized with the left channel, but when the 3rd frame sync comes, a buffer underrun happened as the required left channel data L2 is not available yet in the buffer, so the previous right channel data R1 is transmitted when frame sync is high. And then all other left data are transmitted when frame sync signal is low, so channel swap takes place.

Fig. 3 Tx Data Channel Swap

Below in Fig 4 is...