Browse Prior Art Database

Repair System and Method for ROM Failure

IP.com Disclosure Number: IPCOM000236564D
Publication Date: 2014-May-02
Document File: 5 page(s) / 343K

Publishing Venue

The IP.com Prior Art Database

Abstract

In current IC products, ROM array will be implemented with other IPs to achieve some special applications, which will be used to store critical data and code. ROM test will be run to check the integrity of ROM data/code, and the product will be discarded if test fails. Normally it’s not economic to throw away the silicon or re-TO if the failure number is minor due to design schedule or cost. So it’s imperative to implement on-chip repair feature for ROM failure to improve yield and reduce design cost.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 34% of the total text.

      Repair System and Method for ROM Failure

Abstract:

         In current IC products, ROM array will be implemented with other IPs to achieve some special applications, which will be used to store critical data and code. ROM test will be run to check the integrity of ROM data/code, and the product will be discarded if test fails. Normally it’s not economic to throw away the silicon or re-TO if the failure number is minor due to design schedule or cost. So it’s imperative to implement on-chip repair feature for ROM failure to improve yield and reduce design cost.

1.   Background

       With the development of semiconductor technology and design requirement, ROM array become larger and is widely used to store critical data/code for some special application cases. But the array will be more vulnerable to defect due to its high density and complex structure, which will result in much yield loss. In current practice, ROM test is widely used to check the integrity of ROM data/code; and the product will be discarded if ROM test fails during probe test or final test, which is not economic. So it’s popular to investigate the repair method for ROM array failure by semiconductor companies. In prior arts, some methods are offered, such as redundant row/columns, direct fusing logic to high/low, duplicate memory array, to repair ROM failure, all the methods are to repair ROM failure once or need much silicon redundancy. So a robust method is needed for ease use and flexibility.

       In the article, an effective method and apparatus is offered to repair ROM failure, the apparatus are fully digital and the method is very easy to control, so TE/DE/AE /customers can program the repair information through external interface to check the correctness of repair solution, also the repair solution can be loaded from flash array so that on-chip repair can be achieved. The method and apparatus can improve product yield or reduce NPI schedule.

2.   Proposed diagnosis system for ROM failure

        Normally in IC design, RAM array and external interface should be implemented as basic functions for customers, the external interface can be JTAG/SWD, or other communication interface. So it’s possible to use them in ROM failure repair system. The external interface is used to write repair information to the configuration registers to confirm the repair information can work to fix ROM array failure. Later the repair information can be programmed to flash and can be loaded automatically to repair registers after power up if the repair information has been verified to work, so the product seems no defect to end users. The detailed design diagram is shown in Figure 1. The main components are listed below:

1)      External interface: to load ROM repair information to RAM or register group, e.g. JTAG/SWD or parallel interface, etc.;

2)      Repair control unit: to control repair flow and save repair status;

3)      ROM read control unit: to read and out...