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Method to improve test point probe efficiency using Organic Solder Preservative coated Printed Circuit Assembly boards with Lead Free Formulation

IP.com Disclosure Number: IPCOM000236604D
Publication Date: 2014-May-05
Document File: 3 page(s) / 195K

Publishing Venue

The IP.com Prior Art Database

Abstract

The use of a rectangular test point via shape allows for increased surface area for solder coating which enhances the probe efficiency of a test point.

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Method to improve test point probe efficiency using Organic Solder Preservative coated Printed Circuit Assembly boards with Lead Free Formulation

Disclosed is a novel approach of improving test point probe efficiency by changing the shape of a typical test point.

With organic solder preservatives (OSP) used as surface finish on Lead Free processed printed circuit board assemblies, test point efficiency is greatly impacted due to oxide residues generated, once the printed circuit card starts the manufacturing process. This is more

predominant with small test point vias (less than 24 mils diameter). Due to these residues the test efficiency is reduced to less than 80%. This generates repeat testing, validation of whether the fail is true/false and overall increased test times/lower through put.

To reduce oxidation, plating of the vias during the card assembly process can be developed, however there are limitations depending on the size of the test point via.

Fig.1 shows examples of different stencil designs to plate a round shape via for an OSP printed circuit card. .

Figure 1: Stencil Designs for Plating test point vias

Table 1 shows a summary file of the results using different size vias with such an approach and Fig. 2 shows image results of the plating finish. From the results table, even with such approaches, there is inconsistency in the plating finish condition, thereby not addressing suitably the need for a consistent finish for improving test point probe...