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Noise Reduction System

IP.com Disclosure Number: IPCOM000236607D
Publication Date: 2014-May-06
Document File: 4 page(s) / 118K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a noise cancellation circuit based on feed forward error correction principles. This is a system in which U1 amplifies the noise voltage collected from the decoupled net (after L4) and injects a noise current proportional to the noise voltage back into the same net, but with changed direction.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 52% of the total text.

Page 01 of 4

Noise Reduction System

Noise on the high precision low jitter oscillators used as reference to switch fabrics and PHYs is the main cause of increased bit error rate (BER) in data transmission. The source of noise can be clock drivers mistakenly assigned to the same power rail as the oscillator, noise in the ground plane due to ground loops, insufficient decoupling (which is particularly difficult to implement

below 10KHz, as it needs inordinately bulky components or special power cleaning techniques).

The solution is a noise cancellation circuit based on feed forward error correction principles. With this system, U1 amplifies the noise voltage collected from the decoupled net (after L4) and injects a noise current proportional to the noise voltage back into the same net, but with changed direction.

The transformer T1 is organized in a specific fashion: L2 and L3 are tightly coupled for best feedback and widest bandwidth, while

L1 is calculated for the reflected load seen by the transformer from the termination resistor R5. Because the secondary L3 also sees a large direct current (DC) component, the auxiliary L2 winding serves also as a magnetic flux canceller for the transmission

(L2=L3 for cancellation).

Figure 1: The disclosed solution can be understood in the figure

1


Page 02 of 4

The embodiment above needs to have the noise gain equal but phase reversed to the input noise voltage. The voltage gain of the system is:

Gain (U1) = 1+R2/R1


L2=L3 (or n2=n3 as winding ratios). The impedance ratio seen by the driver is Z primary = (n1/n2)^2*R5

U1...