A Method of Fabricating a DRAM Structure with Capacitor under Access Device
Publication Date: 2014-May-06
The IP.com Prior Art Database
A method is disclosed for fabricating a DRAM structure with capacitor under access device.
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A Method of Fabricating a DRAM Structure with Capacitor under Access Device Disclosed is a method of fabricating a DRAM structure with capacitor under access device.
Fig.1 illustrates the initial step of fabricating the DRAM structure.
As shown in fig.1, the bottom green layer represents the handle wafer and the layer on top of the handle wafer represents a Buried Oxide (BOX) layer. Further, the layer on top of the BOX layer represents a Shallow Trench Isolation (STI) layer and M1 represents a metal deposition.
In the next step the handle wafer is flipped over as shown in fig. 2.
As shown in fig.2, the handle wafer is now at the top and M1 is at the bottom as a result of the flipping.
Fig.3 illustrates a subsequent step, wherein the handle wafer is removed from the top.
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Fig. 4 illustrates a next step in fabrication wherein the structure is patterned and a hole for Deep Trench (DT) contact is etched.
Thereafter, a Silicon on Insulator (SOI) with silicide bottom is exposed as shown in fig.
Here, in the step of exposing the SOI, silicide is optional depending upon subsequent trench fill process.
In the next step, a low temperature n+ poly silicon layer is deposited as shown in fig. 6.
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Alternatively, a metal or a metallic compound is used instead of low temp poly at this step.
Fig. 7 illustrates the next step of patterning the low temperature poly silicon layer using Reactive Ion E...