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SOI Backside Capacitor Structure and Method

IP.com Disclosure Number: IPCOM000236624D
Publication Date: 2014-May-06
Document File: 6 page(s) / 219K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for utilizing the back side of a Semiconductor on Insulator (SOI) wafer so that a capacitor can be added without competing for real estate.

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This is the abbreviated version, containing approximately 100% of the total text.

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SOI Backside Capacitor Structure and Method

Capacitors are highly used in circuits. The requirements of large capacitors are usually done with poly caps (e.g., gate stack cap) or in the back end (e.g., M1 to M2). The implementation of capacitors on the front end competes for area at the silicon level. Additionally, capacitors implemented in the back end occupy the area of circuitry.

The solution is a method for utilizing the back side of a Semiconductor on Insulator (SOI) wafer so that a capacitor can be added without competing for real estate. This is done by processing standard large-sized capacitors that can be chained together. Large banks of capacitance can be available to the circuits built on the wafer. This allows capacitors to be tapped from the front side of the silicon.

The following figures represent the implementation steps in a preferred embodiment.

Figure 1: Finished front/backend process

Figure 2: Rotate and process backside, thin silicon as needed

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Figure 3: Pattern and remove silicon

Figure 4: Deposit node dielectric

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Figure 5: Deposit Conductive Layer, Titanium Nitride (TiN)

Figure 6: Reactive Ion Etch (RIE) to open contact

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Figure 7: Fill node material

Figure 8: Chemical Mechanical Planarization (CMP) down

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Figure 9: Cap material

Figure 10: Connect fill materials

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