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SoC Reset Architecture for Eliminating Reset Domain Crossing Issues along with Die Area Reduction

IP.com Disclosure Number: IPCOM000236751D
Publication Date: 2014-May-14
Document File: 4 page(s) / 760K

Publishing Venue

The IP.com Prior Art Database

Abstract

In the modern era, there is a requirement of achieving high frequency with lower power consumption. Achieving both the targets simultaneously is very difficult and to see silicon alive is like a dream. In a sequential design, if the reset of a source register is different from the reset of a destination register even though the data path is in same clock domain, this will become an asynchronous crossing path and can cause meta-stability at the destination register during asynchronous reset assertion at the source register. This is called Reset Domain Crossing (RDC). For example, if the source register is reset using a functional reset and the destination register is reset using POR (power on reset), then due to RDC, the content of the destination register (that does not get reset during functional reset), cannot be guaranteed across various functional reset assertions. In this paper we present a design to address reset domain crossing issues.

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SoC Reset Architecture for Eliminating Reset Domain Crossing Issues along with Die Area Reduction

In the modern era, there is a requirement of achieving high frequency with lower power consumption. Achieving both the targets simultaneously is very difficult and to see silicon alive is like a dream. In a sequential design, if the reset of a source register is different from the reset of a destination register even though the data path is in same clock domain, this will become an asynchronous crossing path and can cause meta-stability at the destination register during asynchronous reset assertion at the source register. This is called Reset Domain Crossing (RDC). For example, if the source register is reset using a functional reset and the destination register is reset using POR (power on reset), then due to RDC, the content of the destination register (that does not get reset during functional reset), cannot be guaranteed across various functional reset assertions. In this paper we present a design to address reset domain crossing issues.

Fig.1 SoC reset Architecture.

Fig. 1 shows a reset architecture for an integrated circuit.  In the implementation shown, the assertion of reset (any) on IRC (safe clock) is synchronized.  The system clock(s) are gated during any reset event and switch to IRC for the duration reset is asserted.  All of the flops in the circuit are expecting synchronous reset.  IRC propagates through the circuit and initializes the circuit.  Here we have replaced conventional Flip-Flop Cells (with asynchronous reset  pin) with cells that have a synchronous reset pin, and there is a saving in terms of transistor count for a flip-flop.  If we extrapolate this to an SoC then we can say that there is considerable reduction in die size and power.  Using reset in data path, where timing parameters are met, eliminates all Reset Domain Crossing issues.

•       It is assumed that the IP will have the resets, rst[i], for the clock inputs, clk[i]. The wrapper over the IP will have the Proposed Controller (PC), containing the proposed logic for reset and clock modifications. The PC will have corresponding rst_in[i] and clk_in[i] at its input.

•        The PC’s input resets, rst_in[i], are grouped on basis of their assertion/de-assertion. If two resets are always asserted/de-asserted together at the source reset generation module, they will be clubbed in one group. The PC has one counter for each group. All counters are running at IRC clock. The following steps are described for one such counter.

•        The rst_in[i] are synchronized inside the PC at IRC clock (using 2-flop data synchronizer and not the reset synchronizer). When the synchronized reset is detected to be active, a signal, clk_enable, will be de-asserted to ga...