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Scan Flip-Flop Design with Multi-Vt Transistors to Improve Hold Timing

IP.com Disclosure Number: IPCOM000236753D
Publication Date: 2014-May-14
Document File: 5 page(s) / 176K

Publishing Venue

The IP.com Prior Art Database

Abstract

In System-on-Chip (SoC) physical design, many redundant buffers are added to fix hold timing violations in scan mode. These buffers increase design density, make routing congested, and increase chip power. In this paper, a multi-Vt (threshold voltage) scan flip-flop is proposed to fix hold timing violations in scan mode, without impacting functional timing. In a multi-Vt scan flip-flop, threshold voltage of four transistors is increased to provide more hold margin. When replacing the conventional flip-flop with a multi-Vt flip-flop, many hold timing violations may be fixed without adding extra buffers, which saves area and power. Simulation results show 40ps hold timing can be improved, and nearly 1000 buffers can be saved with the multi-Vt flip-flop in 90nm technology.

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Scan Flip-Flop Design with Multi-Vt Transistors to Improve Hold Timing

Abstract

In System-on-Chip (SoC) physical design, many redundant buffers are added to fix hold timing violations in scan mode. These buffers increase design density, make routing congested, and increase chip power. In this paper, a multi-Vt (threshold voltage) scan flip-flop is proposed to fix hold timing violations in scan mode, without impacting functional timing.  In a multi-Vt scan flip-flop, threshold voltage of four transistors is increased to provide more hold margin.  When replacing the conventional flip-flop with a multi-Vt flip-flop, many hold timing violations may be fixed without adding extra buffers, which saves area and power. Simulation results show 40ps hold timing can be improved, and nearly 1000 buffers can be saved with the multi-Vt flip-flop in 90nm technology.

Introduction

With rapid developing in System-on-Chip design, more and more transistors are integrated on a chip, so chip area and power reduction are critical.  In the physical design stage, many redundant buffers are added to fix hold timing violations in scan mode.  These extra buffers increase design density, make routing congested and increase chip power.  This paper proposes a novel scan flip-flop with multi-Vt transistors that can improve hold timing margin in scan mode, compared to a conventional scan flip-flop.  Redundant buffers are saved when fixing scan hold timing so chip area and power are improved.  We implement multi-threshold technology in scan flip-flop, where threshold voltage of four transistors in the scan data path is increased to improve hold timing.  In the physical design flow, hold timing in scan mode can be fixed when replacing the conventional scan flip-flop with the proposed multi-Vt flip-flop, without adding extra buffers. Additionally, the proposed multi-Vt flip-flop does not impact functional mode timing, as it only changes timing in the scan data path.  This makes the proposed multi-Vt flip-flop easy to use and it dies not negatively influence the design.

Design and Implementation

Figure 1 is a schematic circuit diagram of a conventional master-slave scan flip-flop, which has two stages of latches.  When the clock is low, the transmission gate is closed, so the master latch is transparent, the slave latch is locked, and the input data is stored at point “A”.  When the clock changes from low to high, the transmission gate opens, the slave latch becomes transparent, and the data at “A” goes through the slave latch to the next stage.  This data must be transmitted fast enough so that it is caught by the next flip-flop on the next rising edge of the clock.  This is a set-up timing requirement.  Also, this data should propagate so fast that it overwrites the original data of the next flip-flop before the original data goes out safely.  This is a hold timing requirement.

N1

 

N2

 

P2

 

P1

 

A

 

input stage

 

slave latch

 

master latch

 

transmission gate

 

Figure 1....