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Cancellation of delay mismatch based on remote bang bang control loop Disclosure Number: IPCOM000236788D
Publication Date: 2014-May-15
Document File: 9 page(s) / 417K

Publishing Venue

The Prior Art Database


Abstract A distributed bang-bang delay locked loop (DLL) circuit is proposed in which the innovative step is to distribute sub-rate sampling clocks that span a timing interval of 2UI whose samples are then processed by a bang-bang control to synchronize the delay of the remote delay lines to the delay of a centralized clock generator using the same delay cells. The advantage to a conventional approach, where typically the control voltage of the delay cell is distributed, is that the information about the delay is contained in the phase difference of the distributed sub-rate clocks and hence it is much less sensitive to nonidealities such as induced noise because these nonidealities will mainly affect the time domain behavior and much less the frequency domain behavior (note that the bang-bang control acts as a time-to-voltage converter and thus filters out any time domain nonidealities).

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Cancellation of delay mismatch based on remote bang bang control loop

    This publication refers to the problem of cancelling delay mismatches in remote delay lines used for the adjustment of the sampling clock in receivers. Applications such as memory links contain several hundreds of I/Os per memory port in a single chip. Because of the large number of I/Os it is not possible to place the I/Os sufficiently close together such that PVT (process-voltage-temperature) mismatches caused by the different locations on the chip can be disregarded. Moreover, in addition to conventional PVT variations most recent technologies with smaller feature sizes have the problem that traditional matching structures (i.e. symmetrical layout, dummy devices, etc.) reach their limits because some newer technology features (e.g. strained silicon) introduce additional device mismatch issues that depend on the placement of the circuit within the chip.

    In small circuities the delay of a delay line can be controlled with a delay looked loop (DLL) circuit. However, controlling each of the several hundred delay lines with a separate DLL is prohibitive from an area and power perspective. Using a shared delay line in which the analog control voltage is distributed to the remote delay lines might be risky because of induced noise on the analog control signal. The approach presented here tries to circumvent the drawbacks of a shared analog-circuit based DLL and proposes a method, in which the remote delay lines are coupled to the (accurately controlled) phases of a centralized phase lock loop (PLL) circuit by means of a bang bang controlled delay adjustment loop at each remote delay line. In contrast to a shared analog DLL, where a DC control voltage is distributed, we use here for the shared signals sub-rate clocks from the centralized PLL. The essential information for the delay lines is contained in the phase difference between the individual sub-rate clocks. This phase difference is much more insensitive to mismatches than a DC control voltage. The sub-rate operation is used to save power at the signal distribution to the remove delay lines.

    The concept applied in the proposed circuitry is used for souce-synchronous RX sampling such as in DDR memory links. The RX sampling clock is provided externally and is used to derive a multiphase clock that is synchronized to the incoming data. In DDR signalling we switch back and forth from the internal VCO clock to the external RX clock but the data stream is synchronized to the external clock. For the generation of the multiple phase signal that is fed to the RX phase rotator, a remote delay line is used. Because the RX and TX VCO frequencies are the same, we need to lock the delay of the remote delayline to that of the VCO. Currently, an open-loop control voltage copying scheme is used but mismatch is an issue and hence it is desirable to synchronize the delay of the remote delay line to that of a VCO delay stage via a...