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SOI substrate for eDRAM with slip immunity

IP.com Disclosure Number: IPCOM000236812D
Publication Date: 2014-May-16
Document File: 1 page(s) / 20K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to use slip immunity to provide better stability to the Semiconductor on Insulator (SOI) substrate for embedded Dynamic Random Access Memory (eDRAM).

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SOI substrate for eDRAM with slip immunity

Manufacturers use Semiconductor on Insulators (SOI) built on Epitaxial (epi) Silicon (Si) substrate to build logic devices with embedded Dynamic Random Access Memory (eDRAM). When the wafers go through rapid thermal processing, such as spike anneal or laser anneal, the substrate yield and produce slip due to thermal stress. The slip leads to wafer/pattern distortion and causes chip failure. Efforts have been made to strengthen the Si wafer by adding oxygen/oxide or other impurities. However, the improvement has been incremental. Another approach is to improve temperature uniformity in the anneal tool. However, this is a complicated task and becomes more challenging as the wafer size increases.

Silicon on glass substrate has been explored for radio frequency (RF) devices or Micro-Electro-Mechanical (MEMS) applications due to its dielectric and optical properties.

The novel approach utilizes slip immunity of a non-crystalline (glass) or poly-crystalline substrate to provide better stability to the SOI substrate used in the eDRAM Logic fabrication. Compared to single crystalline Silicon, these substrates are less likely to thermally yield during the device processing and thus provide higher chip yield. The glass and poly-crystalline wafers cost less than single crystal Si wafers. The cost savings can be substantial for larger (i.e. 450mm) wafers.

Glass (such as fused silica) wafers or poly-Si wafers can be used for this pu...