Browse Prior Art Database

Timing Analysis of Circuits Containing Dynamic Power Control

IP.com Disclosure Number: IPCOM000236840D
Publication Date: 2014-May-19
Document File: 3 page(s) / 27K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a system to combine representations for a signal Channel Connected Component’s (CCCs) Field Effect Transistors (FETs) and excitations with a power control CCC's FETs and excitations to generate a combined topology and excitation for simulation.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 37% of the total text.

Page 01 of 3

Timing Analysis of Circuits Containing Dynamic Power Control

Previous timing analysis of logic circuits powered through power control Field Effect Transistors (FETs) took one of two approaches. In one approach, the analysis represented the rails controlled by the power control rails as if the power net were ordinary rails. The disadvantages here are that the power rails must then be tied to a single voltage, which degrades the accuracy of simulation. Another approach incorporated the power control FETs as part of the logic circuit through all of the analysis. The disadvantages of this approach are that incorporating the power control FETs in the discovery of Channel Connected Components (CCCs) forces combining all the signal CCCs controlled by one pseudo-rail into one giant CCC, which makes many later steps excessively costly. In addition, incorporating the power control FETs into the logic analysis of a signal CCC complicates the analysis (e.g., by preventing recognition of standard circuit patterns).

The novel idea is to combine representations for a signal CCC's FETs and excitations

with a power control CCC's FETs and excitations to generate a combined topology and excitation for simulation. This involves a system for analysis of digital circuits that breaks apart channel connected components within the circuit across labeled dynamic rails, even though these dynamic rails are connected to channel pins of FETs within the design. The system performs state analysis of these sub-CCC sections of the circuit, treating the dynamic rails as logical constants. In addition, the system recombines sub-CCC components across dynamic rails for simulation.

The dynamic rails are marked as such by a Tcl command (typically called by a pattern match callback), and this marking is used to stop the channel tracing during CCC discovery. This allows the signal CCCs powered by a dynamic rail to be separated from the power control CCC that powers the rail and, if multiple signal CCCs are powered by a shared dynamic rail, to be separated from each other. This separation holds, even though the dynamic rail is connected to a channel pin(s) of the powered signal CCC(s), and is ordinarily traced through in CCC discovery. Instead, it is treated as if it were a rail from the point of view of CCC tracing for signal CCCs. For the purpose of state analysis, the dynamic rails are also treated as logical constants.

In addition, the FET pins on the power control CCC that power the rail are also marked,

which allows combining these FETs into a single power control CCC for this dynamic rail. During the CCC discovery process, each dynamic rail is labeled with the power control CCC that powers it.

In addition to these topological markings, the dynamic rails are also annotated via Tcl commands that add power control CCC sensitizations to these rails. These sensitizations describe constant and switching inputs to the power control CCC and optionally the states of other n...