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Method and System for Providing a Push Pull Driver Output Stage Design using Low Voltage FET Device

IP.com Disclosure Number: IPCOM000236841D
Publication Date: 2014-May-19
Document File: 3 page(s) / 164K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system is disclosed for providing a push pull driver output stage design using a low voltage Field-Effect Transistor (FET) device. The method and system involves designing a 2 device stacking output stage to achieve a same drive function as a 3 device stacking output stage without reliability breakdown exposure.

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Method and System for Providing a Push Pull Driver Output Stage Design using Low Voltage FET Device

Disclosed is a method and system for providing a push pull driver output stage design using a low voltage Field-Effect Transistor (FET) device. The method and system involves designing a 2 device stacking output stage to achieve a same drive function as a 3 device stacking output stage without reliability breakdown exposure.

In accordance with the method and system, 2 device stack output stage using a 1.5V device is designed as illustrated in Fig. 1.

Figure 1

Here, driver output impedance includes 3 legs for p-type Field-Effect Transistor (PFET) pull up and 3 legs for n-type Field-Effect Transistor (NFET) pull down using a 1.5V design. The internal power supply voltage (DVDD) in this case is 3.3V. Normally when 50 ohm drive strength launches onto a 50 ohm transmission line, the initial near end voltage swing is 0.5 times DVDD and eventually reaches a full DVDD swing when reflection comes back to a near end from far end. The DVDD of 3.3V assists in dielectric breakdown of the device.

During Leg 1 a drive strength equivalent to 65 ohm is used instead of a 50 ohm drive strength. This is possible because minimum DC up level for 3.3V is 2.0V and DC down level is 0.8V, according to Joint Electron Device Engineering Council (JEDEC) specs.

As the driver transitions from low to high, initial near end voltage swing is 0.44 times DVDD and later reaches 0.88 times DVDD when the reflection returns from the far end of the transmission line. Thereafter, Leg 1 is shut off and taken over by Leg 3 which is of high impedance. During Leg 3, output level is pulled up to 3.3V DVDD. Leg 6 is switched on along with Leg 3 to create a very small leakage path.

A similar switching sequence is applied for a going down transition. Leg 4 is switched on and subsequently Leg 2 and Leg 5 are switched on simultaneously.

Construction of 3.3V Push Pull Driver designed with a 1.5V device is illustrated in Fig.
2.

1


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Figure 2

The Push Pull driver assists in controlling output stage operation for reliability mitigation on the ouput. The output stage includes normal output stage...