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A Compact Structure for Measuring Diffusion Resistance in finFETs

IP.com Disclosure Number: IPCOM000236844D
Publication Date: 2014-May-19
Document File: 3 page(s) / 173K

Publishing Venue

The IP.com Prior Art Database

Abstract

A compact structure is disclosed for measuring diffusion resistance in finFETs

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A Compact Structure for Measuring Diffusion Resistance in finFETs

Disclosed is a compact structure for measuring diffusion resistance in finFETs. The compact measurement structure disclosed here covers multi-gate, tri-gate, and double-gate CMOS field-effect transistors (FETs) (collectively, there are called finFETs).

In accordance with the structures and corresponding measurement method, finFET drain currents are measured for three cases such as, but not limited to, a non-shared local interconnect, a shared local interconnect and stacked FET case using compact finFET structures.

As illustrated in Figure 1, three (or more) adjacent finFETs are used to measure diffusion resistance.

Figure 1

Figure 2 is a layout for 3 adjacent finFETs shown in Fig. 1. In Figure 2, each of 3 gates can be turned on or turned off separately, each of 4 local interconnects (CAs) (around 3 gates) can be biased independently, and 3 of 4 local interconnects can be sensed separately.

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Figure 2

Figure 3 illustrates architecture of multiple fin-FET(s) arranged in an order for measuring diffusion resistances using a 1x25 probe pad.

Figure 3

As illustrated in figure 4, by applying voltage bias at two different CAs and using one, two, or three FET channels, finFET's diffusion resistance involving shared CA case, non-shared CA case, and stacked FET case can be measured.

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Figure 4

Non-shared CA case: e.g., turn on one gate G23, apply a low voltage (say, ~50 mV) at the p...