Browse Prior Art Database

Reduced Order Pseudo Orthogonal Latin Square ECC

IP.com Disclosure Number: IPCOM000236881D
Publication Date: 2014-May-20
Document File: 9 page(s) / 186K

Publishing Venue

The IP.com Prior Art Database

Abstract

Reliability of the data stored in large memories is very critical and with shrinking process technology, lowered supply voltage and other factors the probability of multi-bit error increases. To reduce the power consumption of the microprocessor the operating voltage is reduced and the minimum operating voltage is set up the reliable operation of the memory [1-Chishti]. The multi-bit error in the memory due to reduced operating voltage sets the limit. All these necessitate the need for multi-bit error correction beyond the Single Error Correction Double Error Detection (SEC-DED).

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 28% of the total text.

Reduced Order Pseudo Orthogonal Latin Square ECC

Abstract:

Reliability of the data stored in large memories is very critical and with shrinking process technology, lowered supply voltage and other factors the probability of multi-bit error increases.  To reduce the power consumption of the microprocessor the operating voltage is reduced and the minimum operating voltage is set up the reliable operation of the memory [1-Chishti].  The multi-bit error in the memory due to reduced operating voltage sets the limit.  All these necessitate the need for multi-bit error correction beyond the Single Error Correction Double Error Detection (SEC-DED).  

Introduction:

The semiconductor process technology which follows the Moore’s law of doubling the number of transistors in successive process technology is shrunk aggressively in terms of the transistor geometry and supply voltage to meet the reliability of the transistor devices.   The shrinking process technology induces more sensitivity to random process variation during manufacturing process and other electrical phenomenon like random telegraph noise, soft error rate in the transistor.  These directly affect the reliability of the data stored in the large memories. To maintain the reliability of the stored data, SEC-DED code like Hamming Code or Hsiao Code is commonly used in today’s memory.   And these codes cannot meet the requirement of correcting multi-bit error in the memory due to above mentioned reasons.

The multi-bit error correction code like binary BCH code Double Error Correction Triple Error Detection (DEC-TED) is available and implemented in memories under specific condition.  Binary BCH codes have minimum or small parity bit requirements with trade-offs for complex decoding hardware logic and long latency [2 Fujiwara].  Alternate prior approaches include orthogonal Latin square code [3 Hsiao], 2D error correction method [4 Kim].  Orthogonal Latin square code is majority-logic decodable code which requires minimal decoding hardware, extremely fast decoding time with trade-off of large parity requirement.  2D error correction method relies on horizontal and vertical parity codes, which adds latency during error correction step.   So trade-off between latency during error correction step and number of parity bits required to be stored is to be decided.  Faster low latency code requires a large number of parity bits which reduces the code efficiency, and high code efficiency code requires complex decoding hardware and large latency.

Latin square was described first by Euler, which is a square array of n elements and each element occurs only once in each row and each column of the square array.  Mutually orthogonal Latin square is at least two Latin square arrays which when combined together at each position of the array forms a unique pair combination that does not repeat. 

First majority decodable code based on mutually orthogonal code was developed by Hsiao et al.,[3...