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A System and Method for Smart Workload Management on Asymmetric Multicore Architectures

IP.com Disclosure Number: IPCOM000236928D
Publication Date: 2014-May-22
Document File: 6 page(s) / 99K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed are a system and method to use Soft Asymmetry and Asymmetry-aware Middleware to manage workloads on asymmetric multicore architectures.

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A System and Method for Smart Workload Management on Asymmetric Multicore Architectures

In recent years, the general trend in microprocessor design has been to partition chip resources onto an increasing number of identical Central Processing Unit (CPU) cores, each of which is capable of simultaneously running one or more hardware threads. Such a design, which is partially enforced by micro-architectural limitations and chip design complexity constraints, potentially provides scalable performance for task-level parallel workloads with many software threads. A major disadvantage of this trend, however, is that applications or tasks that are either single-threaded or made of a small number of threads can only utilize a small fraction of the hardware resources on a chip. As a result, over the past decade, while the number of transistors on a chip have sustained a strong growth rate, single-threaded performance has improved by a sluggish growth rate.

An important class of application that tends to suffer from this trend in microprocessor architecture is batch processing, the performance of which is critical to many large businesses. Common examples of batch processing include billing, end-of-day reporting (for credit card accounts), and extract-transform-load (ETL) in populating data warehouses. Many of these batch applications run in sequence, due either to the nature of the business process or to the original design of the legacy code (i.e., on older systems with a small number of processors).

In order to accommodate different types of workload, some proposals created Asymmetric (also known as single-ISA heterogeneous) Multicore Processors (AMPs) in which a small number of CPU cores are allocated a larger share of the CPU resources than others are. As a result, said cores can be designed specifically to improve single-threaded performance. While preliminary results are promising, showing improvement of overall system performance, such results are somewhat theoretical, as many important aspects of workload and system complexity are not taken into account.

In addition to these hardware proposals, software-based proposals have been developed for using mechanisms such as dynamic CPU over-clocking or selective disablement of some cores on the chip as mechanisms to create faster cores for single -threaded

workloads. However, no single framework allows these software mechanisms to be used in combination with each other based on the specific performance requirements of the single-threaded workload running on the system.

Another major drawback with the current solutions is that the decisions for scheduling a mix of task -parallel and single-threaded

workload on AMP architecture are left to either the CPU firmware to the operating system (OS). This low-level system software has a limited view of how workloads are structured into a collection of threads and how threads are interdependent among themselves. Furthermore, most of the high-level i...