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Structure, Circuit, and Design System for a Merged Triple Well Negative Diode String Application for Negative Bias Power Rail Applications for CMOS, RF CMOS, RF BiCMOS and Image Processsing Technologies

IP.com Disclosure Number: IPCOM000236933D
Publication Date: 2014-May-22
Document File: 2 page(s) / 48K

Publishing Venue

The IP.com Prior Art Database

Abstract

Design a new ESD schema for triple well application by using stack diodes for high speed application. It will require different local isolated well to avoid short in triple well stack diodes.It can be used for charge Pump applications and other high speed circuits and applications that allows the voltages go below the substrate potential

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Page 01 of 2

Structure, ,

Circuit

Circuit, ,

and Design System for a Merged Triple Well Negative Diode String

            and Design System for a Merged Triple Well Negative Diode String Application for Negative Bias Power Rail Applications for CMOS ,

,

RF CMOS

RF CMOS, ,

RF

RF RF

BiCMOS and Image Processsing Technologies

1


Page 02 of 2

Basic Embodiment can be generalized for different applications Merged with Up diode string
Separated from Up diode string

2