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Addressing Identical Devices Using A Single Pin

IP.com Disclosure Number: IPCOM000236949D
Publication Date: 2014-May-22
Document File: 2 page(s) / 55K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed are a method and system that use signal delay to identify common devices in a system. The system works by taking advantage of the Programmable System on Chip (PSoC) on Serial-Attached Small Computer System Interface (SAS) backplanes and adding multiple delays to the ramp of the Inter-Integrated Circuit (I2C) INT_N signal.

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Addressing Identical Devices Using A Single Pin

Current storage system servers have a number of Serial-Attached Small Computer System Interface (SAS) backplane options, and those options can go in a number of locations within a chassis. As the backplane changes location in the chassis, it needs to be able to identify and change or update:

1. The bay location so that the storage enclosure processor (SEP) on the backplane can correctly label the drives in a desired order

2. The Inter-Integrated Circuit (I2C) address so as to not clash with others on the I2C bus; else it needs to be on a different I2C bus altogether

This current approach relies on a number of straps to be on the system planar to inform the backplane of location. In addition, the current approach establishes route individual I2C busses to each backplane to avoid contention on the I2C bus. This approach costs pins and wires in connectors as well as I2C muxes on the planar.

The solution is a method and system that uses signal delay to identify common devices in a system. The novel approach uses the already existing I2C interrupt (INT) line that goes to each backplane in a daisy chain fashion with a delay added between each backplane connector. A timer in the backplane's Programmable System on Chip (PSoC) starts at power-on and uses the time to see the INT high as the backplane's trigger to set its chassis bay location and I2C address.

The system works by taking advantage of the PSoC on SAS backplanes...