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FPGA dynamic weighted reconfiguration

IP.com Disclosure Number: IPCOM000236980D
Publication Date: 2014-May-23
Document File: 2 page(s) / 25K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method and system that balances Field Programmable Gate Array (FPGA) image weights to select the FPGA image that best fits a system's configuration.

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FPGA dynamic weighted reconfiguration

A Field Programmable Gate Array (FPGA) image has a finite amount of data per boot. The disadvantage of this is that if a component/module inside the FPGA is not used, because a peripheral is not present or for other reasons, that allocated resource is wasted and not recovered. This is because at compile time there is no way of knowing what devices will be present for a given system at run time. For example, some systems may have four memory modules present and others may have 48. The FPGA designer must allocate resources for up to 48 Dual In-Line Memory Modules (DIMMs). Other modules in a design are sacrificed because of the resource demand of the memory logic.

An algorithm is needed that loops through all available FPGA images and selects the best-suited FPGA image for the system.

The novel contribution is a method and system that balances FPGA image weights to select the FPGA image that best fits a system's configuration.

To implement the method and system to select the FPGA image for a system's configuration in a preferred embodiment:

1. FPGA powers on 2. FPGA boots first image 3. FPGA scans inventory and compares needed function to what current image offers 4. FPGA writes an image "weight" into Non-Volatile Random Access Memory (NVRAM) for use later 5. FPGA boots next image 6. Repeat steps 3, 4, and 5 until all FPGA images have been weighed against current system inventory 7. Last image compares its current weight to oth...