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Method and system to auto disable and enable clock ports

IP.com Disclosure Number: IPCOM000236989D
Publication Date: 2014-May-23
Document File: 2 page(s) / 53K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is an auto-sensing clock chip that intelligently detects a downstream device’s loss of power and turns off clock output, preventing board level leakage.

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Method and system to auto disable and enable clock ports

Existing clock generator devices in the industry have discrete clock enable pins to individually control the clock outputs. These devices rely on writes to an internal register to enable/disable an individual clock. For multi-output generators, sequencing the clocks per design requirements can be difficult.

Figure 1: Commonly used multi-port clock generator chip [*]

When a clock is driven into a powered OFF device, it draws more current than if it is driven into a powered ON device.

A clock generator that can detect when the downstream device is powered off, and has the ability to disable the clock going into it, is needed.

The novel contribution is an auto-sensing clock chip that intelligently detects a downstream device's loss of power and turns off clock output, preventing board level leakage. This design includes a clock chip that embeds its clock "enables" by placing a weak pull-up resistor inside the receiver's Input/Output (IO) mechanism. The clock generator measures current draw at each one of its clock outputs. (Figure 2) Thus, it can power-off clock output when it detects a noticeable power increase.

The lab work process is:

1. Designer runs tests in the lab and documents current draw when system is on and off for each clock output

2. Designer programs memory inside the clock chip to power off at varying trip points

To implement the method and system to auto disable and enable clock ports:

1. Whe...