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Level Shifter with Predefined Status without Valid First Power Supply

IP.com Disclosure Number: IPCOM000237020D
Publication Date: 2014-May-27
Document File: 3 page(s) / 140K

Publishing Venue

The IP.com Prior Art Database

Abstract

Level Shifters are widely used in various complex multi-voltage integrated circuits or SOC designs where signals are transmitted from one voltage domain to another. Conventional level shifters usually suffer from a severe issue, i.e., the level shifter output turns to high impedance (unknown status) when the first power supply is not available. In a complex SOC design, it is very common that during power up, the Power Management Circuit (PMC) may have different turn-up times, and this unknown status will cause severe logic issues in the downstream logic of the second power domain. Various improvements have been proposed to resolve the issue but each has certain problems such as more complexity, slow speed, etc. In this paper, we propose a high performance level shifter with a simple modification that resolves the high impedance state issue.

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Level Shifter with Predefined Status without Valid First Power Supply

Abstract:

Level Shifters are widely used in various complex multi-voltage integrated circuits or SOC designs where signals are transmitted from one voltage domain to another. Conventional level shifters usually suffer from a severe issue, i.e., the level shifter output turns to high impedance (unknown status) when the first power supply is not available. In a complex SOC design, it is very common that during power up, the Power Management Circuit (PMC) may have different turn-up times, and this unknown status will cause severe logic issues in the downstream logic of the second power domain. Various improvements have been proposed to resolve the issue but each has certain problems such as more complexity, slow speed, etc.  In this paper, we propose a high performance level shifter with a simple modification that resolves the high impedance state issue.

1.    Problems with conventional Level Shifter

A typical level shifter circuit is shown in Fig. 1. A general problem associated with it is called “power sequence issue” where VDDH will be ready much earlier than VDDL. In such case, both output Q and QB will be HighZ, which will result in all downstream logic statuses to be unknown or unexpected. In some cases, it may result in unrecoverable information loss or even device damage. One example is an unexpected Flash erase/program where Flash content will be lost. Another example is where a charge pump is enabled but without control, then voltage could be pumped up until the device is damaged.

Fig. 1 - Conventional Level Shifter

2.    Proposed Level Shifter to overcome the power sequence issue

There are some proposed techniques to tackle the level shifter issue, like using pull down or up devices controlled by POR (Power On Reset) or other control signal to force the output to an expected logic state before VDDL is on. A few oth...