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Enhanced Interactive Debug Tool for Parasitic Extraction of Integrated Circuits

IP.com Disclosure Number: IPCOM000237073D
Publication Date: 2014-May-29
Document File: 8 page(s) / 90K

Publishing Venue

The IP.com Prior Art Database

Abstract

Described is an enhanced interactive debug tool for parasitic extraction of integrated circuits.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 52% of the total text.

Page 01 of 8

Enhanced Interactive Debug Tool for Parasitic Extraction of Integrated Circuits

The layout of integrated circuits require parasitic extraction to ensure high-speed performance. Extraction software can provide parasitic resistances and capacitances for every net in the form of an extracted netlist. Through the simulation of the extracted netlist, the circuit designer examines the circuit performance. It is desirable to have detailed information of the resistance and/or capacitance of critical nets in the high-speed signal path. Further, it is helpful to know and understand the source of these parasitics so that the layout can be improved and, therefore, performance of the design can be improved as well. This invention provides tools that enable the circuit designer to understand the interactions between the layers of the design that cause each of the parasitics that the extraction tool has generated.

    This invention provides the circuit designer a method to select net(s) of interest, then examine the detailed sources of all parasitics on that net on a per-layer basis and then to further select the layers of interest which allows for the identification of the exact location in the layout of the detailed parasitic. It should be noted that since the extraction tool generates the parasitics for the nets in the design that the detailed information that this invention shows currently exists but is extremely difficult to find and use. Also, this invention details a parasitic capacitance process but it could and should also be used for parasitic resistance and inductance.

    The current method for improving circuit performance post layout is shown in Figure 1 below:

Figure 1

1


Page 02 of 8

    The new process using this invention is shown in Figure 2 below where the highlighted box is the enhanced approach which should reduce the number of layout design iterations to complete this pro...