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Browse Prior Art Database

Method of forming high Ge% CMOS

IP.com Disclosure Number: IPCOM000237116D
Publication Date: 2014-Jun-03

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to form a high Germanium (Ge) percentage (%) in a Complimentary Metal-Oxide Semiconductor (CMOS).

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This is the abbreviated version, containing approximately 66% of the total text.

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Title

Method of forming high Ge% CMOS

Abstract

Disclosed is a method to form a high Germanium (Ge) percentage (%) in a Complimentary Metal-Oxide Semiconductor (CMOS).

Problem

A high Germanium (Ge) percentage (%) FIN is attractive for 7nm, especially for positive Field Effect Transistors (PFET). However, a high Ge % has a temperature restriction. This leads to the issue of forming a low resistance source/drain that requires high temperature processing.

Solution/Novel Contribution

The novel contribution is a method to form a high Ge% in a Complimentary Metal-Oxide Semiconductor (CMOS).

Method/Process Invention Process Flow 1


1. After Silicon (Si) or low Ge% SiGe FIN formation


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2. After low Ge% SiGe cladding


3. Oxygen Hydrogen(OH) rich oxide (such as High Aspect Ratio Process (HARP)/Flowable Oxide (F-OX)) gap fill and Chemical Mechanical Planarization (CMP)


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4. Dummy a-Si and gate hard mask (HM) deposition


5. Polycarbonate (PC) and spacer Reactive Ion Etching (RIE)


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6. FIN recess followed by epitaxy (epi) growth


7. Source Drain (S/D) implant followed by high temperature dopant activation


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8. Oxide fill


9. Silicon Nitride (SiN) etch back


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10. Oxide CMP


12. SiN deposition


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14. SiN open


15. Amorphous silicon (a-Si) removal


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16. Oxide recess for final high Ge% SiGe FIN reveal


17. After high-k/metal gate stack formation and SiN cap formation

Embodiment 1:

Both negative Metal Oxid...