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Method and System for Providing Buried Polish Stop Layers to Isolation Trenches in Silicon on Insulator (SOI) Substrates

IP.com Disclosure Number: IPCOM000237145D
Publication Date: 2014-Jun-05
Document File: 2 page(s) / 60K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system is disclosed for providing buried polish stop layers to isolation trenches in silicon on insulator (SOI) substrates.

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Method and System for Providing Buried Polish Stop Layers to Isolation Trenches in Silicon on Insulator (

((SOI

SOI) )

Disclosed is a method and system for providing buried polish stop layers to isolation trenches in silicon on insulator (SOI) substrates. The method and system utilizes buried polish stop layers, such as, but not limited to, un-doped oxide, SiN, and SiCN for providing enhanced SOI substrate structures and improve uniformity of pre-metal dielectric. Buried polish stop layers also improves contact etching processes required for SOI substrates.

In accordance with the method and system, as shown in Figure 1, a buried polish stop layer such as for example SiN at a depth of 2.0um is applied to the isolation trenches of SOI substrates. Thereafter, the SiN layered SOI substrate is capped with USG at a depth of 200nm which provides improved SOI structures and uniformity of pre-metal dielectric.

Figure 1

Consider a scenario, as shown in Figure 2, a buried USG polish stop layer is applied at a depth of 0.7um to the isolation trenches of SOI substrates. Subsequently, USG layered SOI substrate, during Chemical Mechanical Polishing (CMP) of CA-tungsten, prevents oxide loss and improves oxide uniformity for CA RIE.

Figure 2

Advantageously, the buried polish stop isolation trenches helps in obtaining optimized performance metrics such as, but not limited to, low harmonics, low insertion loss, and

Substrates

Substrates

1


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