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Method and System for Implementing a Deep Trench Capacitor in Three Dimensional Through Silicon Via Keepout Area for Electrostatic Discharge Protection

IP.com Disclosure Number: IPCOM000237146D
Publication Date: 2014-Jun-05
Document File: 3 page(s) / 103K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system is disclosed for implementing a Deep Trench Capacitor (DTCAP) in three dimensional (3D) Through Silicon Via (TSV) keepout area for Electrostatic Discharge (ESD) protection.

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Method and System for Implementing a Deep Trench Capacitor in Three Dimensional Through Silicon Via Keepout Area for Electrostatic Discharge Protection

Disclosed is a method and system for implementing a Deep Trench Capacitor (DTCAP) in three dimensional (3D) Through Silicon Via (TSV) keepout area for Electrostatic Discharge (ESD) protection.

Existing ESD requirements are 200 volt (V) Human Body Model (HBM), 25V Charged Device Model (CDM) and10V Machine Model (MM). In accordance with the existing ESD requirements, the method and system provides two options. In the first option, only DTCAP is used, wherein the method and system covers the ESD requirements based on one or more initial assessments/simulations. In the second option, the method and system utilizes additional ESD devices and modifies designated area around the TSVs.

Fig. 1 illustrates an exemplary implementation of the method and system disclosed herein.

Figure 1

Figs. 2 and 3 illustrate simulation results of the method and system disclosed herein using 200V HBM ESD event with 10 nano Farad (nF) capacitors.

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Figure 2

In Fig. 2, a spectre transit simulation for HBM ESD event is illustrated. The spectre transit simulation proves that capacitance between VDD and GND net will provide a protection during an ESD event.

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Figure 3

In Fig. 3, the curve illustrates the simulation results and shows that the voltage in

VDD180 does not increase more than 1.8V when the net capacitor valu...