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Method and apparatus for interrupt arbitration in a Multi-Core system

IP.com Disclosure Number: IPCOM000237149D
Publication Date: 2014-Jun-05
Document File: 4 page(s) / 421K

Publishing Venue

The IP.com Prior Art Database

Abstract

Method of interrupt arbitration in a multi-core system is disclosed. A multi-core SOC has numerous interrupt sources, each assignable to a single or multiple cores for ISR (Interrupt Service Routine). An interrupt controller receives interrupts events from various sources in the SOC and manages the interrupt notification (delivery) and completion process on their behalf.

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Method and apparatus for interrupt arbitration in a Multi-Core system

Abstract— Method of interrupt arbitration in a multi-core system is disclosed. A multi-core SOC has numerous interrupt sources, each assignable to a single or multiple cores for ISR (Interrupt Service Routine). An interrupt controller receives interrupts events from various sources in the SOC and manages the interrupt notification (delivery) and completion process on their behalf.

I.     BACKGROUND

T

he proposed interrupt arbitration scheme is for a multi-core system among multiple sources, each with several levels of priority. The interrupt arbitration scheme is orthogonally scalable in terms of number of interrupt sources it can arbitrate amongst, number of priority levels per interrupts source, and number of interrupt destination cores.

A multi-core SOC has numerous interrupt sources, each assignable to a single or multiple cores for ISR (Interrupt Service Routine). An interrupt controller receives interrupts events from various sources in the SOC and manages the interrupt notification (delivery) and completion process on their behalf. Each interrupt source has its priority in the system and at any given time, the highest priority interrupt must be selected and sent to a particular core. A single interrupt source can further be mapped to multiple cores/threads (multicasting).

If a core is servicing an interrupt, only an interrupt with a priority higher than the one being serviced can interrupt the execution of the ongoing ISR. The interrupt controller incorporates an arbitration scheme that selects an interrupt to be sent to a core based on the above mentioned criteria. The arbitration scheme should be scalable in terms of number of interrupt sources, interrupt priority levels and interrupt destination.

Figure 1 shows an interrupt controller for a multi-core system.

Figure 1: Block Diagram of Interrupt Controller in Multi-core system

As the number of sources and priority levels per source increase it becomes increasingly difficult to meet the desired frequency of operation and area numbers of the interrupt controller. The problems and limitations of conventional approaches to design interrupt controllers for multi-core systems are described below.

Cascading structure to determine highest priority interrupt

Figure 2 represents a typical logic used to determine the highest priority interrupt for a particular destination core. 16 priority levels per source are considered for this case.

Figure 2: Cascade structure to determine highest priority interrupt

Each 4-bit comparator in the above diagram does a priority comparison between two interrupt sources. The winner is then compared with the next interrupt source and so on. As the number of sources or the number of priority levels increase, the size of the comparator increase and it becomes difficult to meet timing after a certain number of levels.

II.     Proposed Method

The above mentioned limitations are overcome using the prop...