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Early Detection of Peak Voltage Drop and EM Issues

IP.com Disclosure Number: IPCOM000237152D
Publication Date: 2014-Jun-05
Document File: 3 page(s) / 321K

Publishing Venue

The IP.com Prior Art Database

Abstract

Clocks, being the most high activity portion of a design, are critical for dynamic voltage drop and are Electro Migration prone. In the design implementation, all such voltage drop issues on high activity nodes are checked through activity file (VCD). The timing information is used to generate VCD, which is merged with clock activity. But in a design cycle by the time it is checked for clock tree, the design cycle usually moved ahead of clock tree. And any such change is not possible during that stage.

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Early Detection of Peak Voltage Drop and EM Issues


Clocks, being the most high activity portion of a design, are critical for dynamic voltage drop and are Electro Migration prone.  In the design implementation, all such voltage drop issues on high activity nodes are checked through activity file (VCD).


The timing information is used to generate VCD, which is merged with clock activity. But in a design cycle by the time it is checked for clock tree, the design cycle usually moved ahead of clock tree. And any such change is not possible during that stage.                             

Fig. 1

It leads to design changes in clock path, which results in many timing violations near the end of cycle closure. Also there might not be much space available to put de-capacitance to fix the EM. Moreover, VCD based solution is very much use-case dependent, which might not cover each individual clock node. Below suggested way works on the static timing concept that makes it more robust and pessimistic. It helps in early detection of such cases. Figure 1 shows the impacted EM issue in clock path due to overlapping of timing window.

In this paper we share an algorithm for early detection of the EM and generate a fix within the design cycle. This will help resolve clock related changes further ahead in the design cycle. The algorithm is timing window based and not dependent on any activity. This way it statically detects the possibility of EM and provides a pessimistic and robust solution for EM detection.

 In the algorithm described the timing window information is used to check the clock signal activity overlap under a possible overlapping window in terms of timing and distance.  Fig. 2 shows a flow chart of the algorithm.

The algorithm is used just after clock tree synthesis is done. Steps involved are explained below.

1)      Timing Window Extractor: New property is introduced for all clock elements. And min and max clock arrival i...